Larger vias used for the stitching to provide more copper, providing better conduction capacity & continuity between planes (larger hole size = more copper around circumference of cut through plane)
Smaller vias used for signals and other areas to make it easier to fit vias closer together, i.e. for ESP signal fanout, due to large hole to hole clearance of 0.5mm required by JLCPCB
DECISION UPDATE: Learned that larger vias only provide marginally better current capacity. It is better to have more vias closer together (more vias actually provides more current capacity, closer together reduces inductance)
- For this board, larger vias will be replaced with the smaller vias to have all vias be the same size. Number of vias may be increased for certain power pours/ground stitching to improve current capacity & thermal performance. RF vias will be made smaller, but otherwise won’t be changed as spacing is already only 1/50th of 2.4GHz wavelength, much below the 1/20th maximum spacing recommended in Infineon app note linked above
- Discord conversation resulting in this decision: https://discord.com/channels/776618956638388305/1112251506339618836/1151579646274588742

expresslrs-gemini-tx

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