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Power nets must be defined such that their regulator topology and/or upstream source is clear. For example, the nets associated with a buck converter should have a prefix with “BUCK”.

For example, a +3.3V net and +12V net should could be named PP3V3 and PP12V0 respectively. Where PP is short for Power Pole.

Power Rails

• PWR_3V3

• VBATT_48V

• VBUS_12V

Buck Converter Nets

For example, consider a 12V to 3V3 buck converter. The bootstrap net should be named:

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Digital Nets

GPIO Nets

For example, a 3V3 LL 3.3 V LL (logic level) GPIO for commanding the select pin of a 2:1 multiplexer from an MCU should be named:

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With A as the transmitter and B as the receiver, for 3V3 LL3.3 V Logic Level, we have:

• UART_A_TO_B_TX_3V3

• UART_B_TO_A_TX_3V3

Notice that both nets are defined to be transmitting. Tx and Rx are relative to the device so those terms are avoided to avoid ambiguity. The only difference is the direction from the transmitter and receiver. The “TX” can be omitted because it is implied. To understand how UART works refer to UART - Universal Asyncrohonus Transmitter Reciever .

SPI Net

With A as the master and B as a slave, for 3V3 LL, we have:

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