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CC pins are trace width impedance matched to 50 Ohms on the bottom layer.
Routing them on the bottom layer makes it so that there is no via stub. It also means the traces have to be wider, as there is no coupling below. Seeing as they will also carry power for VCONN, these were OK to be made wide.
The lines are routed in such a way that they will NOT cross a plane split in the board to reduce concern of EMI. As a direct example, CC2 (the lower pin) goes around the VBUS pour and and only where ground would otherwise be. There are ground vias placed near the traces when possible.
Drain pour is connected to the bottom layer.
The DRAIN pins on the TPS25730 are part of the internal FETs on the IC package. Since these will spend the most of their operating time closed, it’s a good idea to give the heat-generating power loss from RDS_ON a thermally conductive pad to be able to leave the board quickly. Vias are placed as recommended by TI.
USB-C VBUS input routing is on the top and bottom layers.
The VBUS input runs through L1/L4, connected through six vias for up to 20V 5A max power draw. While each 8mil hole/16mil diameter via should do around 1.7A, six is recommended by TI and is a good conservative count.
Top and bottom layers are exposed to the air, making them the most thermally conductive and are great to route high power nets on. This is due to how current limits on PCBs are often actually thermal limits.
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