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Introduction
Who?
Reserved for Daniel Puratich co-op
Context
COTS ELRS PWM Receiver: https://betafpv.com/products/elrs-micro-receiver
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This makes R equal to 130 ohms. We can find and place the appropriate resistor into the design.
Schematic Design Review
Net Naming Guidelines - Making sure each power net in the design has an appropriate label. Crucial for PCB layout time.
Electrical Terminology - A sort of review for terminology in EEhttps://drive.google.com/file/d/1S0Mzs7YdFf1vUP41wHp3JbctDb-8adoG/view - Simulating the input filter to make sure the capacitor configuration is working harmoniously
Clean up schematic styling - following industry/WARG standards for a clean and readable final schematic
Next, can let EFS team know of the design and to review that the PWM outputs from the ESP8285’s pins are possible and appropriate. Once that is complete, an EE lead can do a final review, and PCB layout can begin.
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Input Filter Simulation
Mainly working off of https://drive.google.com/file/d/1S0Mzs7YdFf1vUP41wHp3JbctDb-8adoG/view, an impedance analysis plot across various frequencies was made to verify the function of the decoupling capacitor network. seeing as V/I = Z, the plot is labelled with V(v1)/I(V1). As equivalent series inductance and resistance values vary depending on frequency, many of the ESR/ESL values were taken at the 1MHz point of frequency (since the buck IC has a switching frequency of 1.2MHz), or taken from a general rule of thumb (I pulled these ESL values from Daniel’s presentation). Values from Murata SimSurfing.
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The majority of the capacitor network is built with MLCCs (multi-layer ceramic capacitors). These have low inductance and resistance but have high Q-values, making them good at targeting specific frequencies (higher frequencies) that need to be brought down within the impedance plot.
Electrolytic capacitors, on the other hand, are often higher energy, but also have higher (equivalent series) inductance and impedance. This means that they are slower to react to sudden changes in current or voltage. They have a lower Q, meaning they are able to target a wider, often lower range of frequencies. They are physically larger as well, many packaged in a radial cylinder form.
Many of the recommended schematics for this buck IC only added a few barebones capacitors. This would likely be fine, but due to our use case having sensitive RF applications for communication with the fixed-wing plane, as well as the plane having 6 PWM outputs (which could introduce high frequency noise), the additional filtering is welcome.
PCB Layout
Basic Guidelines
This board will be 61x30.5mm, with an area of 1860.5mm^2. According to Mounting Hole & Patern Specifications, this makes the board a “medium” size, meaning it will need M2 screw mounting holes. These have 2.40 mm hole diameter and 4.20mm annular ring diameter and will go in the corners of the board. Each hole will need 8 appropriately sized vias equally spaced out. We can add the holes themselves as a pad.
PCB Layers
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Following this 4-layer stackup with no impedance control from JLCPCB, our manufacturer.
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Buck Converter
The following are layout guidelines and examples from the TPS56424x buck IC datasheet.
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