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Power Configuration
Resistor Dividers
The TPS25730 has 4 ADCIN pins that each control a parameter of the requestable voltage and current. Each divider must take voltage from LDO_3V3 and step it down to a target value to be read by the pin. The specific ratios translating to the decoded values are shown in the table below.
The ratio is calculated using: Ratio = Rdown / (Rup+Rdown).
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Decoded ADC Values
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If the source device cannot supply voltage between the minimum and maximum voltages set by pins ADCIN1 and ADCIN2 ORthe operating/maximum current is violated, then the controller will signal a capabilities mismatch and run the CAP_MIS pin high.
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TVS2200 for 20V model, clamping begins at 22V. TVS1400 for 12V model, clamping begins at 14V.
the LDO_3V3 output pin from the IC is linked to the GPIO pins (e.g. PLUG_FLIP), and can only supply max 5mA, with 1mA max per GPIO pin
I2C line is likely to be unused and will be DNP’ed during assembly. The PD IC is not V/I configurable through I2C as wellpower configurable through this line.
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The ADC pins are configured as Variants in Altium and are viewable through the Altium 365 project viewer.
Layout
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Some notable decisions:
CC pins are trace width impedance matched to 50 Ohms on the bottom layer.
Routing them on the bottom layer makes it so that there is no via stub. It also means the traces have to be wider, as there is no coupling below. Seeing as they will also carry power for VCONN, these were OK to be made wide.
The lines are routed in such a way that they will NOT cross a plane split in the board to reduce concern of EMI. As a direct example, CC2 (the lower pin) goes around the VBUS pour and and only where ground would otherwise be. There are ground vias placed near the traces when possible.
Drain pour is connected to the bottom layer.
The DRAIN pins on the TPS25730 are part of the internal FETs on the IC package. Since these will spend the most of their operating time closed, it’s a good idea to give the heat-generating power loss from RDS_ON a thermally conductive pad to be able to leave the board quickly. Vias are placed as recommended by TI.
USB-C VBUS input routing is on the top and bottom layers.
The VBUS input runs through L1/L4, connected through six vias for up to 20V 5A max power draw. While each 8mil hole/16mil diameter via should do around 1.7A, six is recommended by TI and is a good conservative count.
Top and bottom layers are exposed to the air, making them the most thermally conductive and are great to route high power nets on. This is due to how current limits on PCBs are often actually thermal limits.
PCB Design
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Input/output connectors labelled for a pleasing aesthetic presentation.
Inverted text silkscreen for better readability.
I2C lines (SCL, SDA) and GND test points are labelled on the back to save space.
Voltages are labelled on the back of the board. This is so that after assembly, the appropriate voltage configured on the specific board can be circled by sharpie for easy identification.
Horse on a chair sitting on a porch, viewing a storm. Hard image.
This was actually hard to get into Altium - in order to reduce lag and have the appearance of greys, the image was downscaled to 350px and then converted to greyscale and dithered with Floyd-Steinberg algorithm (Normal mode) in GIMP.