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Finally we have the series NMOS. This circuit is a series NCH FET in the power path. This circuit requires a charge pump to saturate the FET, however, implementing this is done by many ICs so you don’t need to do this yourself! Further, some ICs, especially for lower power applications simply put the NCH FET inside the chip itself. Realistic NCH FETs for this application could have RDSon is between 20m ohm all the way down to 0.1m ohm so much less than a PCH. If you crave even lower ESR you can simply run a few of these FETs in parallel to reduce losses even more! This means the FET can have extremely low power consumption (of course less than the PCH solution) though don’t forget to include the losses of powering the controller IC itself. When following a datasheet’s instructions designing one of these circuits can be surprisingly doable. Adding an IC to the circuit will increase cost, but it is often worth it. Component count will end up about the same or more than the series PCH circuit. Another thing to note about this is a lot of ICs will have other features you may want as well (i.e. input overvoltage protection and/or an electronic fuse / overcurrent protection). An example of this implementation with a controller IC and external NCH FETs is given by 12V->5V @ 5A Buck Converter Board .
There are other options, but these are most common. Feel free to add more to this document if you find something nice! All of these options can be simulated in LTSpice or Simplis for a deeper understanding (though getting a model for a specific IC can be annoying). Shoutout to this conversation for inspiring me to write this up :d
Other resources: