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Introduction

  • Inspiration

  • Who

  • Where

  • Timeline

    • Desired for Competition in 2025 so ideally boards are fully assembled by end of Fall 2024.

    • Hardware design will be completed before midterms for midterm PCBA order in F24 term.

      • Daniel Puratich is intend on fighting to make this happen and is encouraging anyone to help by breaking this down into green comments for subtasks in the schematic (if viewing in the future please see the version history in Altium 365 for how I did this).

  • Features we aren’t adding but considered

    • no ELRS

      • ELRS changes a lot quickly

      • could be saved for a future revision

      • can be done via a simple connector to any COTS module

    • no cameras

      • mounting a camera makes placement complicated

  • Features

    • Begin from RPI Interface Rev B

      • Keep the UART “killswitch” and one UART passthrough for the RPi to FC direct

        • Being implemented in the stm though instead of the hardware switch

        • This is being done to avoid running out of UARTs on the STM and to avoid hardware complexity

        • UART forwarding can be done with DMA so it can be fast and not very resource intensive.

        • Justification for this as a feature is given in RPI Interface Rev B .

      • Keep UART LED indicators

        • this is nice for debugging

        • costs some board space

        • could be DNPed in a final version

      • Keep CAN circuit

        • this can be used to control the lighting system if we wanted to?

        • Could also connect to pixhawk for mavlink over CAN if we’re able to do the required firmware to make this solve.

    • Add LED features

      • Some neopixels on the board might be nice.

      • Leds on the pwr rails since I have space.

      • IR detector so we could use one of those cheap remotes to control LEDs.

    • Analog Monitoring

      • STM has some spare analog pins so might as well use them

      • temperature and voltage monitoring

    • Add an LTE modem to RPi interface rev c

    • Change buck converter to support 48V input so we can connect VBATT

      • this makes architecture decisions and harnessing easier

    • Switch STM32

      • STM take in the three uarts form quectel

      • The other STM is smaller and doesnt have enough UARTs for this

      • STM will communicate with the RPi over SPI

    • Increase board size a bit

      • this turns the board into a full normal RPi hat

      • This is required for cooling for the LTE module and a simple USB connection for the LTE hat

  • Why

    • Unlimited range & unlimited datarate is really attractive even if it comes at the cost of some weight and some power consumption.

    • Maintaining C2 link is required for flight so full reliance on ELRS is scary even if we have overwhelming evidence for it’s reliability

    • This board is an RPi hat because there is good COTS software support for the Quectel that runs on the RPi. The presence of the STM allows us to experiment with using the embedded proccessor but this will take a lot of time to bring up.

    • Eventually this board can be used as a standalone without the RPi to save weight. We want the Pi for airside compute now, but could be cool to try it in the future

    • The reason for the STM is that it’s real time and guaranteed run time and low power operation. See here.

    • Dual bucks is done because it’s hard to find ICs that do up to 7 A without external FETs & compensation. I want this to work right off the bat though in theory higher efficiency is achievable

  • Standards

Block Diagrams

All Possible Configurations:

Component Selection

Trivially selected components aren’t really mentioned here, but some of the more complex stuff is noted here.

Modem Re-Selection

Regional Band Compatibility

We initially selected the EG915N-EA, which only includes bands optimized for usage in Europe and Asia.

This model has band 7 but is missing 12, 13, and/or 71 (as per discussion from Nathan in #rpi-interface-rev-c). Band 7 is (1) limited to certain networks and (2) is 2600MHz, which is fast, but limits ranged performance. 12, 13, and 71 are lower frequency channels and will provide more channels to switch into, as well as better range.

To watch for when selecting a new modem: We want a pin compatible model with the EG915N, as we have already done extensive layout considerations around this footprint, and we want to maintain the 2 supported SIMs. We want bands 7, 12, 13, and 71.

Other models

image-20241122-174300.png

https://www.quectel.com/lte-iot-modules/

https://www.quectel.com/download/quectel_eg91xqbg9xeg9x_series_compatible_design_v1-1/

image-20241123-225352.png

EG915N-EA

https://www.quectel.com/download/quectel_eg915n_series_hardware_design_v1-2/

Quectel_EG915N_Series_LTE_Standard_Specification_V1.3

BG95M3

https://www.quectel.com/download/quectel_bg95_series_hardware_design_v1-6/

Quectel_BG95_Series_LPWA_Specification_V2.0-4-1.pdf

EG915Q-NA / EG916Q-GL

https://www.quectel.com/download/quectel_eg91xq_series_hardware_design_v1-3/

Quectel_EG916Q-GL_LTE_Standard_Specification_V1.1

Comparison Table

Model/Specs, DigiKey CA Link

EG915N-EA (original model)

BG95M3 Series

EG915Q-NA Series

EG916Q-GL Series

$/ct (DigiKey)

~$34.52 CAD

~$50.54 CAD

~$54.23 CAD

~$63.99 CAD

Stock (DigiKey)

~200

~1,236

~236

~37

Pin-to-pin compatible?

-

Kind of, footprint includes an arc-ed pad

Yes. (need confirmation from more eyes)

Yes (with few changes, listed below).

LTE Bands

LTE-FDD: B1 / 3 / 7 / 8 / 20 / 28

Cat M1: B1 / 2 / 3 / 4 / 5 / 8 / 12 / 13 / 18 / 19 / 20 / 25 / 26 / 27 / 28 / 66 / 85

Cat NB2: The above and 71, without 26 and 27


Spec Sheet

LTE-FDD: B2 / 4 / 5 / 12 / 13 / 66

LTE-FDD: B1 / 2/ 3/ 4/ 5/ 7/ 8/ 12/ 13/ 18/ 19/ 20/ 25/ 26/ 28/ 66

LTE-TDD: B34 / 38/ 39/ 40/ 41

# of SIM Interfaces

2

1

2

2

Specs Screenshot

image-20241122-180252.png

image-20241122-180142.pngimage-20241122-182641.png

image-20241122-184757.png

Notes

The package of the EG916Q devices is slightly larger and heavier. The pins are placed in physically identical positions.

image-20241122-200406.pngimage-20241122-200237.pngimage-20241122-200207.png

Notable pinout differences between EG915N-EA and EG916Q-GL (includes all EG91xQ-series devices):

  • GNSS debug pins on Q model (109, 110)

  • AUX_RTS and AUX_CTS removed on Q model (now RESERVED pins)

  • USIM2 no longer has a DET pin on Q model (no card detect)

  • Q model uses previously RESERVED pins for CAM SPI functionality (95, 78, 97, 98, 115, 93, 94)

  • Q model has backup power pins for the GNSS antenna (117, 118, 112)

  • Pins for SLEEP and WAKEUP have been renamed (among others)

  • MIC-related pins have been removed (now RESERVED pins: 119, 121, 122, 126, 120)

Layout

Collection of hardware design guideline excerpts from various component datasheets.

Quectel_EG915N_Series_Hardware_Design_V1.2.pdf

image-20241118-190753.pngimage-20241122-214038.png

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