7 - Constraints of PCBs

Manufacturing process

A PCB is typically just layers of copper separated by dielectric.

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A 4-layer stack-up.

As PCB designers, we typically pick how many layers we want, how thick we want the layers to be, how we want to connect between the layers, and the shapes and traces we want cutout from the copper.

A PCB manufacturing company will then etch out the copper we don’t want based on the design file we make in Altium for each signal layer. Then, the copper layers are sequentially laminated with dielectric to create the PCB stack. Via holes are drilled throughout the process. This can happen at the end of the manufacturing process for PTH (plated-through hole) vias, or before the 2 outermost layers are laminated for blind/buried vias in HDI (high-density interconnect) designs.

This is, very basically, how a PCB is designed. By drilling, etching, and separating out different parts of copper, we can form physical representations of all of our electrical nodes/nets in the schematic.

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Cross-section view of a multi-layer stack-up with PTH vias.

We route traces on these layers of copper, which are essentially etched “wires” that connect different components. We also make connections between layers by using vias, which are holes drilled in the PCB which are electroplated with copper to make inter-layer connections.

Non-ideal conductors

When we think about a wire or an electrical connection, we typically think of it in an ideal manner, where a wire or electrical connection is a “perfect conductor” and neither experiences nor receives external effects from the environment. This is, unfortunately, not reality.

Copper traces on a PCB are not pure perfect conductors, as they have a small unwanted resistance to them. Current flowing through a wire produces a magnetic field around it, which makes the trace/wire a tiny inductor. A trace (or any conducting material) on a PCB is also a capacitor, since there are many other conductive surfaces near it at different voltage levels with dielectric in between, that it behaves like an unwanted capacitor.

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These are called parasitic elements, since they are unwanted and are not intentionally included in the design. In high-speed PCBs, these parasitic elements must be accounted for to maintain strict propagation delay and signal timing requirements.

Example: Sharp load step

Typically in a PCB, you have an IC or some electrical load that is switching (changing states from on → off, or vice versa) often. This means that your circuit/PCB can quickly go from not needing any current to needing a very large amount. If we recall that an inductor resists sudden changes in current, you may begin to see why this can become an issue. Imagine if all your traces that lead to devices on your PCB have parasitic inductance – this would harm the transient response of those signals.

When a circuit turns on or switches instantaneously (sometimes called a “load step”), the load is suddenly demanding (“sinking”) a large amount of power. Visualizing this as the rising edge of a square wave representing load current, one can imagine the harmonics of the rising edge would be extremely high frequency.

To allow time for a source to respond to a load transient like the one above, we use capacitors. A capacitor acts like a small reservoir of energy, which can store charge closer to your load than the external power supply that may power the PCB. Capacitors are highly reactive at high frequencies (X_C = 2*pi*f*C), which allows them to be effective sources of power during sudden temporary changes in electrical load. They also have many use cases in filtering noise.

A hypothetical design scenario

Based on the following information, what can you deduce about the best placement for a decoupling capacitor? Should the decoupling capacitor be placed in position A, close to the input power supply, or in position B, close to the IC that is demanding the power? Think about the priority of each of the components when placing components for your PCB.

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Frequency response

When dealing with digital or analog circuits, we have to remember that signals that travel on PCB traces are actually compositions, or sums, of many sinusoidal signals. The image below shows that a square wave (which could easily be a clock signal or some data) is made up of many sine waves with different amplitudes and frequencies. A simple step function may seem like a low frequency function because it happens once, but in reality, the step function rise time is closely related to the frequencies involved in the rising edge.

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This means that we need to be careful of inductance and capacitance since they affect the impedance of our PCB traces, and impedances are frequency dependent. The equation for impedance can be seen below. This equation in the context of a PCB trace is basically saying that the resistance to the AC part of your signal is composed of the regular DC resistance of a trace plus some inductive reactance - capacitive reactance value.

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Return currents

The diagram below shows a 5V input supplying current to a board, which follows a hypothetical trace (path outlined in red), eventually meeting the IC. The return current (ground) is shown as the yellow path through an internal ground plane in the PCB board. This return path is predictable, as the yellow diagonal line is the absolute shortest path back to the power source. Current follows the path of least resistance (impedance), and the shorter the path, the less equivalent parasitic resistance is encountered.

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However, this path is not true in all cases. The yellow return current path looks fine for low frequencies (slow changing voltages), but sometimes the path that return current takes is not always the shortest path, but rather the path with the lowest impedance. The second diagram above shows that there is capacitive coupling between the 5V trace and the ground layer beneath it. This makes sense; since there is a 5V difference with dielectric separating the two potentials, there is effectively some sort of capacitance.

Remember that there is always parasitic capacitance and parasitic inductance. When current travels through copper it generates a magnetic field and this causes some small amount of inductance.

If we take a look at the diagram below, we can analyze the return current path under two situations: low frequency and high frequency signals. We see 5V copper trace on the top layer (shown in red) that goes to an IC. A via on the other side of the IC attaches it to the ground layer underneath. Underneath is an entire copper ground layer, and the yellow and blue lines show different return paths.

At low frequencies, impedance is minimized at the yellow return path since inductance plays less of a role at low frequencies. At high frequencies, the inductance in the yellow path increases the impedance. The blue return current path, while also containing parasitic inductance, shows that there is some capacitance between the 5V trace and the GND layer underneath it.

Looking at the impedance equation, we can see that this actually decreases the total impedance, as the reactance of the capacitance counteracts the reactance of the inductance. This means that the overall impedance is lower than the yellow path.

So at higher frequencies, return currents tend to follow the path of the initial trace.

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A simulation can be seen below of current in the ground plane underneath a U-shaped trace. At low frequencies, the GND return current is determined by the shortest path that minimizes DC resistance. The higher the frequency, the more the signal current path follows the trace. Recall that a square wave is actually composed of sine waves of many frequencies, and the sharper the square wave, the higher the frequency. So, even a system that doesn’t have any fast oscillating sine waves still likely has some rising edges in its system, which means that this effect of return current still applies in most circuits.

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What happens if there's no ground near/underneath our signal? The next diagram demonstrates this. It shows a black trace on a top layer made of copper going from the connector and into a resistor, which then goes down a via into the green ground copper layer. The red loop shows the current path from the connector input, through the black copper trace and the return current path that the current takes on the ground layer.

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If we have a split in the ground plane or no nearby ground for return current to come back, it will have to take a longer route which creates something called a larger current loop.

Remember that current that travels in a loop creates a magnetic field so a constantly changing current creates a constantly changing magnetic flux through the loop area. Also remember that a constantly changing flux in a loop of wire creates a constantly changing current in the loop of wire.

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