Gate Drivers

Owned by Lance Bantoto (Deactivated)
Last updated: 2021-08-13 by Kevin Li
18 min read

Preliminary Concepts

Power MOSFET Theory and Operation

The metal-oxide-semiconductor field-effect transistor (MOSFET) is the most commonly used transistor in electronic circuit design today. The MOSFET has many useful properties. Listed below are a few:

  • Scalability

  • Low turn-on current

  • High switching speeds

  • High off-state impedance

Internal Structure

The MOSFET consists of four terminals:

  • Drain (D)

  • Source (S)

  • Gate (G)

  • Body (B)

Oftentimes, the body terminal is shorted to the source terminal, rendering the MOSFET as a three terminal device. A basic diagram of the MOSFET is shown in the figure below:

MOSFET Basic Internal Structure Diagram

Let us define a few parameters:

  • VGS: Voltage between the gate and source terminals of the MOSFET

  • VDS: Voltage between the drain and source terminals of the MOSFET

  • Vth: The MOSFET threshold voltage

Operating Regions

The MOSFET has three basic regions of operation that may be defined with a few simple expressions. These regions are listed below:

  • Cutoff

  • Linear

  • Saturation

Cutoff Region

The MOSFET operates in the cutoff region when the following condition is satisfied:

In the cutoff region, the MOSFET is OFF and no conduction occurs between the drain and the source.

Linear Region

The MOSFET operates in the linear region when the following conditions are satisfied:

In the linear region, the MOSFET is ON and behaves similar to a resistor controlled by the gate voltage with respect to both the source and drain voltages.

Saturation Region

The MOSFET operates in the saturation region when the following conditions are satisfied:

In the saturation region, the MOSFET is ON and behaves similar to a current source controlled by the drain and gate-to-source voltages.

Parameters

The figure below demonstrates a common MOSFET modal highlighting the terminal-to-terminal capacitances and gate resistance.

We define the parameters below:

  • CGS: The capacitance between the gate and source terminals. This value is fairly constant

  • CGD: The capacitance between the gate and drain terminals. This value varies heavily with the gate-to-drain voltage, drain-to-source voltage, and applied frequency.

  • CDS: The capacitance between the drain and source terminals. This value varies heavily with the gate-to-drain voltage, drain-to-source voltage, and applied frequency.

  • CISS: A measure of the input capacitance between the gate and source terminals with the drain and source terminals shorted (CISS=CGS+CGD)

  • COSS: A measure of the output capacitance between the drain and source terminals with the gate and source terminals shorted (CISS=CDS+CGD)

  • CRSS: The reverse transfer capacitance measured between the drain and gate terminals with the source terminal connected to ground (CRSS=CGD)

  • RG: The resistance in series to the gate terminal

To account for variation in the capacitance value with respect to voltage, it is common to see a gate charge curve for greater context. Gate charge values relate to the charge stored within the interterminal capacitances. Gate charge is useful because it factors in the changes in capacitance with respect to voltage during a switching transient. Shown below is an example of a MOSFET gate-charge curve.

Shown below is another example of a MOSFET gate-charge curve with a few important parameters labelled.

The gate charge parameters are defined as follows:

  • QG: The total gate charge required to raise the gate-to-source voltage to the specified value (4.5V and 10V are commonly used voltages)

  • QG(th): The charge required from 0V to the threshold voltage of the MOSFET. Current will start to flow from the drain to source at the threshold voltage

  • QGS: The charge required from 0V to the Miller plateau voltage. At the plateau voltage the drain to source voltage will start to slew.

  • QGD: The charge required to move through the Miller region. The name Miller region is derived from the fact that the gate-to-source voltage stays relatively constant during this period as the reverse transfer capacitance is charged. The MOSFET VDS slew occurs during this period as the MOSFET becomes enhanced.

Turn-On Behavior

The behavior of the MOSFET when certain voltages and currents are applied becomes clearer when it is understood that a specific amount of charge is required to bias the gate to a certain voltage. Consider the repeated figure below.

Provided below is a simple walkthrough of the MOSFET Turn-On Response curve from left to right:

  • The curve begins with the gate-to-source voltage increasing a charge is supplied to the gate terminal.

  • When the gate-to-source voltage reaches the MOSFET threshold voltage, current begins to flow from the drain terminal to the source terminal.

  • The gate-to-source voltage then becomes fairly constant as the MOSFET moves through the Miller region. During the Miller region, the drain-to-source voltage drops.

  • After the Miller region, the gate continues to charge until it reaches the final drive voltage.

Simple Slew-Rate Calculation

Since the MOSFET VDS slew occurs during the Miller region, the Miller charge (QGD) and gate drive strength can be used to approximate the slew rate. The first assumption that should be made is that an ideal constant current source is being used for the MOSFET gate drive.

In reality, calculating the precise MOSFET VDS slew rates from parameters and equations requires precise knowledge of the MOSFET, the board, package parasitics, and specific information on the gate drive circuit.

Slew Rate Example Calculation

Provided below are datasheet parameters for the CSD18532Q5B:

The figure below shows a DRV8701 Smart Gate Driver driving a CSD18532Q5B at 24V. The DRV8701 device is configured for the 25mA source current setting.

The waveform shows an approximate 312ns slew rate that matches closely with the first order approximation calculated with the equation below:

Gate Drive Current

Peak gate drive current and average drive current are two key parameters when designing a switching power-MOSFET system, such as a motor drive.

Peak Gate Drive Current

The peak gate drive current is the peak current that the gate driver can source or sink to the power MOSFET gate during the turn-on and turn-off periods. This value is primarily responsible for how fast the MOSFET can slew.

Rise and Fall Time Example Calculation

The DRV8701 supports a peak source current of 150mA and a peak sink current of 300mA. Assuming that a DRV8701 is driving a CSD18532Q5B at a sufficient voltage, we can calculate the rise and fall times as shown:

 

Average Gate Drive Current

The average gate drive current is the average current required from the gate driver when switching the power MOSFETs constantly. As previously described, the amount of charge to switch a power MOSFET is small (44nC), but when switching the MOSFET in the kHz range, this charge will average into a constant current draw from the gate driver supply. The average gate drive current is given by the expression below:

Note that NMOSFET is the number of MOSFETs switching.

Average Gate Drive Current Example Calculation

Let us assume we are driving six CSD18532Q5B at a switching frequency of 45kHz. We can calculate the average gate drive current as shown:

Smart Gate Drive

This section describes the various challenges encountered in motor gate driver systems and the different features implemented in TI Smart Gate Drivers to help solve these challenges.

Slew Rate Control for EMC and Power Loss Optimization

Adjusting and tuning the MOSFET VDS slew rate is often the first and most critical challenge faced in motor gate driver system design. The MOSFET slew rate directly impacts multiple performance factors, including:

  • Switching power dissipation

  • Radiated emissions

  • Diode recovery

  • Inductive voltage spikes

  • dV/dt parasitic turn-on

Multiple methods exist to tackle these challenges and they all share a direct dependency on slew rate. Slower slew rates improve performance in radiated emissions, voltage spikes, and parasitic coupling, but will increase power dissipation. Optimizing the factors of this tradeoff are crucial for every motor system designer.

IDRIVE Implementation

Precisely controlling the current applied to the MOSFET gate lets the user make a reasonable calculation for and adjust the MOSFET VDS slew rate. TI Smart Gate Drivers have an adjustable gate drive current scheme in many of the motor gate drivers to easily control the MOSFET slew rate. This adjustable gate drive current parameter is called IDRIVE.

MOFSET Pre-Driver Switch IDRIVE Implementation Method

The most common implementation method of IDRIVE is shown in the figure below.

A MOSFET pre-driver switch is enabled between the gate and the voltage supply to manage the current directed to the external power MOSFET gate. To control the current to the gate of the external MOSFET during the VDS slew, the Smart Gate Driver takes advantage of several MOSFET properties:

  • If the switch (pre-driver MOSFET) can be operated in the saturation region, the current to the external MOSFET is limited to a fixed value

  • As the external MOSFET moves through the Miller region, the gate-to-source voltage plateaus and stays relatively constant

Using these properties, the Smart Gate Driver can ensure that the correct voltage bias is applied to the gate of the pre-driver switch and that it is in the saturation region for the duration of the Miller charging period. Since the gate of the external MOSFET appears as a short (AC voltage applied to a capacitance), the source or sink current is limited to the saturation current of the switch. By using multiple switches, the Smart Gate Driver can alternate between different current levels during normal operation as shown below:

Current Source IDRIVE Implementation Method

The second method to implement the IDRIVE feature uses current sources instead of switches. This implementation occurs in applications that require very precise and consistent control of the external MOSFET VDS slew rate across device, voltage, and temperature. This architecture is especially important in applications that are EMI sensitive and depend on characterizing the system at a specific slew rate.

IDRIVE Slew Rate Control

The IDRIVE feature lets the VDS slew rate be adjusted at any time without adding or removing external components to the system. This allows the switching performance of the MOSFET to be fine tuned.

The persistence plot below shows the effect on the VDS slew rate from adjusting the IDRIVE setting on a TI Smart Gate Driver. The MOSFET VDS slews from 24V to 0V and the slew rate decreases as IDRIVE is adjusted across seven levels (10mA to 70mA in 10mA increments) of gate source current.

The following figures show additional signals of the MOSFET while it is being enhanced. The current from the Smart Gate Driver and the Miller region of the external MOSFET is clearly shown when the VDS slews.

Recalling from a previous section, if a sufficiently ideal current source and an accurate MOSFET QGD parameter are available, an approximate calculation for the VDS slew rate can be made. In the table below, the calculated VDS slew rate for several IDRIVE settings. We neglect series gate resistance and non-idealities here.

The scope plots below are for the different IDRIVE values shown in the table above.

EMI Optimization Example

Electromagnetic interference (EMI) is high frequency noise generated from the switching of the power MOSFETs. Ideally, the square-voltage waveforms generated by the power stage are clean ground-to-supply signals.

MOSFET parasitics and PCB layout can cause undershoot and overshoot voltages that ring on the switching output. This parasitic ringing can occur at frequencies much higher than 1MHz, often directly in sensitive spectrum bands. Additionally, the fundamental edge rate of the MOSFET switching can translate into noise in the high frequency spectrum.

These parasitics can be tackled with the following considerations:

  • Improving PCB layouts

  • Adding snubbers

  • General design enhancements

  • Tuning the switching frequency of the power MOSFETs

IDRIVE provides an ideal way to tune the motor gate drive system by providing simple control of the MOSFET slew rate through either a register write or one resistor setting which users select the optimal setting that minimizes efficiency losses while keeping an acceptable EMI level.

The data listed in the table below provides an actual example of the Smart Gate Driver IDRIVE feature. The peak readings of an EMI engineering scan from 30MHz-200MHz with a Smart Gate Driver at different IDRIVE settings. As the IDRIVE current is decreased, the peak scan readings are also decreased.

If we analyze the output waveforms with an oscilloscope, it can be seen that a frequency oscillation is induced on the switch-node with higher IDRIVE settings. Zooming in at a higher resolution shows the effects on the end of the rising edge. By reducing the IDRIVE, the oscillation is almost completely removed which gives an example of how its architecture can be used in a real-world application.

Shown below are the results from the radiated emissions engineering scans for each of the IDRIVE settings.

Slew Time Control

On certain TI Smart Gate Drivers, such as DRV8718-Q1 and DRV8714-Q1, an advanced function is provided to regulate the switch-node slew time with closed loop feedback. While open loop control methods described earlier are often sufficient for MOSFET slew rate control, occasionally tighter control is required by the system.

This is because key MOSFET parameters can vary due to manufacturing and system condition variations. Parameters such as the MOSFET gate charge will vary from device to device and even on the same device, changes in the system voltage and temperature will cause these parameters to shift during operation.

Closed loop slew time control loop is required to resolve these challenges. Closed loop slew time control operates by monitoring the switch-node slew time and adjusting the IDRIVE current setting continuously during the operation of the driver in order to achieve a configured target setting. An example of the slew time control loop is shown in the figure below.

Robust MOSFET Switching Through TDRIVE State Machine

MOSFET Handshaking

It is crucial to avoid cross-conduction (“shoot through”) conditions in switching MOSFET systems to prevent damaging the power MOSFETs or system supply. Cross-conduction occurs when both the high-side and low-side MOSFET are enabled at the same time. A low impedance path is introduced between the power supply and ground. The path lets a large amount of current to flow, which can potentially damage the external MOSFETs or power supply.

Cross-conduction typically occurs when switching from the low-side to high-side (or high-side to low-side). A delay occurs from when the input signal is received to when the external MOSFET is off related to the internal propagation delay and slew rate of the MOSFET. If the opposite MOSFET is enabled before this delay period finishes, cross-conduction may occur.

A simple method to prevent this issue to add a period of timing before enabling the opposite MOSFET. This period of time is called dead time. Increased dead time decreases the efficiency of the motor driver because of diode conduction losses.

TI Smart Gate Drivers monitor the MOSFET VGS voltage with an intelligent TDRIVE state machine that incorporates internal handshaking to provide an optimized amount of dead time for the switching MOSFET system. The VGS monitors make sure the opposite MOSFET in the half-bridge is disabled before enabling the commanded MOSFET.

In addition to cross-conduction protection (shoot-through), this method can provide system performance benefits by reducing the period of diode conduction. Conduction losses of the MOSFET internal body diode are typically worse than standard MOSFET conduction losses and decrease the overall efficiency of the system.

MOSFET Gate-Fault Detection

The TDRIVE state machine lets the Smart Gate Driver detect fault conditions, such as a stuck low or stuck high condition, on the gate of the external MOSFET. Gate faults could be caused by a defect or failure in the power MOSFET gate oxide or a pin fault failure on the gate driver itself. By monitoring the voltage and managing the current to the external power MOSFET, the Smart Gate Driver can detect and report when an abnormal event (partial short, short circuit) has occurred on the MOSFET gate.

The TDRIVE gate drive timer makes sure that under abnormal circumstances, such as a short on the MOSFET gate or the inadvertent turning of a MOSFET VGS clamp, the high peak current through the Smart Gate Driver and MOSFET gate is limited to a fixed duration. The concept is outlined below:

  1. The Smart Gate Driver receives a command to enable the MOSFET gate.

  2. A strong current source is then applied to the external MOSFET gate and the gate voltage starts to rise.

  3. If the gate voltage has not increased after the TDRIVE period (indicating a short circuit or overcurrent condition on the MOSFET gate), the Smart Gate Driver signals a gate drive fault and the gate drive is disabled to protect the external MOSFET and gate driver.

  4. If a gate drive fault does not occur, the Smart Gate Driver enables a small current source after the TDRIVE period to keep the correct gate voltage and decrease internal current consumption.

dV/dT Turn-on Prevention

The internal TDRIVE state machine also provides a mechanism for preventing dV/dt turn-on. A dV/dt turn-on is a system issue that can occur when rapidly slewing the high-side MOSFET. When the switch node rapidly slews from low to high, it can couple into the gate of the low-side MOSFET through the parasitic gate-to-drain capacitance (CGD). The coupling can raise the gate-to-source voltage of the low-side MOSFET and enable the MOSFET if the voltage crosses the MOSFET threshold voltage (Vth). If the low-side MOSFET enables while the high-side MOSFET is on, cross conduction occurs.

The TDRIVE state machine works to prevent dV/dt turnon which can lead to cross conduction in the external half-bridge. By enabling a strong pulldown on the low-side MOSFET during high-side VDS slew, the Smart Gate Driver can provide a low-impedance path for parasitic charge that couples through the parasitic capacitance of the low-side MOSFET gate to drain capacitance (CGD). This impedance path prevents a rise in the gate-to-source voltage of the low-side MOSFET, which could potentially enable the MOSFET while it is supposed to be off.

The TDRIVE state machine disables the strong pulldown after the switching period and moves to a weak pulldown to decrease the chance of damage to the Smart Gate Driver or system in the scenario of a gate-to-drain short of the external low-side MOSFET. By limiting the period of high current, the Smart Gate Driver can prevent damage to itself and limit further damage to the system.

System BOM Reduction

A Smart Gate Driver provides the ability to decrease the system BOM and required board area through integrating key components of the motor gate drive system. A typically Smart Gate Driver block diagram is shown below:

The first key point to note is the adjustable gate drive current sources for the turn on and turn off control of the external MOSFET. These are adjustable in order to provide the typical slew rate control compensation that would be done with external components. Typically, the RSOURCE and RSINK resistors manually adjust the impedance between the gate driver and MOSFET gate. The diode lets the rise and fall VDS slew rates to be individually adjusted. In a Smart Gate Driver, the adjustable gate drivers integrate this functionality.

Additionally, the internal pull down resistors replace typical external resistors to implement this functionality. The RPULLDOWN resistor makes sure that the MOSFET stays disabled even when the gate driver is inactive.

Lastly, integrated VDS and VGS comparators are provided for every gate driver output. These comparators manage the overcurrent detection for the external MOSFETs and detect potential gate drive faults. These comparators and their various settings can be configured directly through the Smart Gate Driver SPI or hardwire settings.

Propagation Delay Optimization

System Challenges

Another common challenge in motor gate driver system design is managing propagation delay and its impact to the switching performance of the system. Propagation delay has two key parameters that impact overall switching performance:

  • The overall delay from input to output

  • The mismatch from turn-on to turn-off

These two parameters will directly impact the minimum and maximum duty cycle, frequency range, and duty cycle step resolution. Good switching performance is important to achieve optimal performance from the motor in regards to speed and torque control.

While most gate drivers will specify their delay and mismatch parameters, they are only one part of the overall input to output system. They other key part is the MOSFET switching delay itself. At high slew rates, the MOSFET contribution to propagation delay and mismatch will often be minimal as compared to the driver, but at slow slew rates, as often found in EMC sensitive systems, the MOSFET can be a main contributor.

Looking further at a typical MOSFET datasheet, we can begin to understand how the MOSFET parameters impact the overall propagation delay. The capacitance parameters across voltage for the CSD18532Q5B are shown below:

It is important to understand how these parameters change over voltage as it can be used to determine both the QGD and QGS of the MOSFET. Oftentimes the QGD and QGS will be specified as an electrical characteristic of the MOSFET, but this is typically specified at a given VDS which may not be representative of the actual system conditions.

Referring to the equations below, we can determine a more accurate QGD value as a function of CRSS and VDS. This is integrated over VDS as this is dynamically changing during the QGD charging as shown in the figure above. We can then find a more accurate QGS as a function of CISS and VDS. This is multiplied as VDS is relatively static during the QGS charging as shown above.

From QGD and QGS we can determine the MOSFET contribution to propagation delay and slew time:

Using the CSD18532Q5B MOSFET example again, we can calculate an approximate QGD and QGS. Assuming a 12V power supply, QGD is approximately 1.2nC and QGS is approximately 6.9nC. Further assuming a 1μs slew time, we can calculate an Isource of 1.2mA. From this, we can calculate the approximate propagation delay to be 5.75μs.

In summary, we can see that QGS >> QGD and this typically holds true for most MOSFETs. We can also conclude that at slower slew rates the propagation delay time becomes a significant factor in switching performance. If using a 20kHz PWM signal, a greater than 5μs propagation delay is already more than 10% of the overall period.

Propagation Delay Reduction

On certain TI Smart Gate Drivers, such as DRV8718-Q1 and DRV8714-Q1, an advanced function is provided to reduce the propagation delay for the MOSFET charge and discharge by using a dynamic current control. scheme. This scheme reduces propagation delay in order to support a wider PWM duty cycle range and also to reduce thermal dissipation in the MOSFET as it moves through the residual charging region after the miller charge region. This is shown in the figures below. The dynamic current control has several regions including a pre-charge current (IPRE_CHR) for reducing propagation delay (tDON/OFF), a drive current (IDRVP/N) for slew rate control, and a post-charge current (IPST_CHR) for residual charging.

In order to implement robust dynamic current control, the Smart Gate Driver uses an adaptive scheme to learn and predict when the switch node is going to enter the slewing region and preemptively adjust the gate drive current. A predictive scheme is required as the typical delays from using direct feedback with comparators could impact the slewing region itself.

In this adaptive scheme, the controller modulates the current for a proportion of the programed propagation delay and then monitors at which point the switch-node slews. Based on whether the switch-node slews early or late the pre-charge current is then adjusted up or down as shown in the figure below.

Every PWM cycle, the pre-charge current (IPRE-CHR) is updated based on the switch-node (VSH) slew timing until the desired propagation delay (tDON) is reached.