6S Power Module

Owned by Daniel Puratich
Last updated: 2024-10-28 by Andrew Chai
7 min read

Introduction

 

Electrical Architecture

Features:

  • Buck + LDO (Power Module)

  • Current Sense

  • Active Cell Balancing

  • Cell monitoring and measurement (SoC calculations)

  • MCU for custom cell balancing algorithm + cell input calculations + interfacing with IC

  • CAN circuitry

Elec System Design

Component Sourcing

Buck:

image-20240721-193004.png

  • Exposed Pad (Vin Exposed pad - pin number on symbol??? is this ok in general for a vin pin to be an exposed pad?)

  • What should I use for switching frequency? From what I’ve seen online, higher switching frequency means I can use smaller inductors and capacitors but increases losses.

    • Going to use 1M switching frequency for reduced board space. Seems to be a typo/mistake in the datasheet as the 5000 should actually be 55000 or 52500, so in theory RF should be around 47.5 to 50 kOhms. I will be using a 47k resistor because Yageo do not offer a 46.6k

image-20240710-191337.png

  • Vout = 0.8 * (1 + R1/R2)

  • 5V output requires standard resistor values of: R1 = 52.3k, R2 = 10k (recommended from datasheet) this yields around 4.984V

  • alternatively, R1 = 53.6k yields around 5.088V (Would it be better to design for slightly higher than 5V for some error compensation?)

  • For some error tolerance and to compensate for losses, 5.2Vout will be used so R1 = 54.9k and R2 = 10k to produce around 5.19Vout

  • standard resistor values source: https://www.rfcafe.com/references/electrical/resistor-values.htm

Component Calculations

Buck Converter Calculations ← Calculations can be found here

https://www.ti.com/lit/an/slva477b/slva477b.pdf?ts=1721655939318&ref_url=https%253A%252F%252Fwww.google.com%252F

 

Input Capacitor

  • Ideally <1% of Vin for ripple voltage so 0.01* (20V or 26V) ripple range: 0.2V to 0.26V

  • Cin should be between 3.75uF and 2.39uF, 3.3uF should be fine

    • Will use 4.7uF to reduce input ripple voltage, this gives around 0.52%-0.82% input ripple voltage

 

Output Capacitor

  • From online, it seems around 1% of Vout ripple voltage is desirable (lower is better obv)

  • Since we’re using X5R and X7R capacitors I’m assuming ESR can be ignored???

  • Vout is 5V so 1% is 0.05V would be preferred

  • For ripple current 0.2,0.3,0.4 of Iout = 4A (0.8A, 1.2A, 1.6A → 2uF, 3uF, 4uF)

  • higher capacitance = less ripple voltage = better

  • Standard Capacitor Values & Color Codes

    • Standard cap values within range: 2.2uF, 3.3uF

    • I will be choosing 3.3uF (at 0.3Iout ripple current, this is around 0.9% of output voltage (45mV)

    • 4.7uF also works and this reduce the ripple voltage even more, this gives around 0.61% output ripple

    • Should be rated for >4A and >5V

 

Inductor Selection (Section 3 of the TI document)

Loop Compensation Resistor and Capacitor

  • With 4.7uF cap output, and around 10kHz bandwidth (this is 1/100 of the switching frequency but the stack exchange Low cost buck SMPS with IC AOZ1284 - 5V x 4A - values for COMP pin answer verified with sims that around 10kHz is a more realistic achievement (Need to get this verified)

  • Rc is about 2050 ohms so 2k resistor should work

 

  • RL is the load resistor value, load resistance = Vout/Iout = 5/4 = 1.25Ohms

  • CC is around 2.9375nF so a 3nF cap (3.3nF will be used)

Others

  • Enable Pin is high between 1.2V and 5V so 3.3V from the AFE IC will be supplied to this pin (filter cap needed??)

  • Soft start Pin: “A soft start process begins when the input voltage rises to 3V and voltage on EN pin is HIGH. In soft start process, a 2.5µA internal current source charges the external capacitor at SS. As the SS capacitor is charged, the voltage at SS rises. The SS voltage clamps the reference voltage of the error amplifier, therefore output voltage rising time follows the SS pin voltage. With the slow ramping up output voltage, the inrush current can be prevented. Minimum external soft-start capacitor 850pF is required, and the corresponding soft-start time is about 200µs.”

    • will be using 10nF cap, was available on the WARG component library (relatively similar value)

  • Schottky Diode:

    • To reduce the losses due to the forward voltage drop and recovery of diode, Schottky diode is recommended to use. The maximum reverse voltage rating of the chosen Schottky diode should be greater than the maximum input voltage, and the current rating should be greater than the maximum load current.

    • Using the SK54A-LTP Diode which is already in the warg component library

    • rated for 40V @ 5A which should be enough for 26Vin and 4A current out

Cell Monitor IC

AFE Design:

  • Does D23 need to be implemented if we are using an XT90 Connector?

  •  

STM32

  • Using the STM32L431KCU6 (the same one from Meghan’s CAN adapter circuit)

  • Will be using the CAN adapter circuit @Meghan Dang, with STM32, 8Mhz oscillator, and connectors

  • https://datasheet.ciiva.com/pdfs/VipMasterIC/IC/SGST/SGST-S-A0003208311/SGST-S-A0003208311-1.pdf?src-supplier=IHS+Markit

  • On Pin definitions of the STM datasheet (starting at Page 59), the UFQFPN32 model is the one used for this design

    • ADC pins used (Voltage, temp readings from AFE)

      • Pin 8 [PA2] → ADC_REF2 (reference voltage for AFE2)

      • Pin 14 [PB0]→ ADC_REF1 (reference voltage for AFE1)

      • Pin 11 [PA5]→ VCOUT_1 (voltage data 1)

      • Pin 10 [PA4]→ VIOUT (current data)

      • Pin 15 [PB1]→ VCOUT_2 (voltage data 2)

    • Instead of hooking the SPI lines from both AFEs up together, 2 separate SPI ports are used on the STM32 (I2C1and I2C3)

      • Pin 19 [PA9] → SCL1 [I2C1_SCL]

      • Pin 20 [PA10] → SDA1 [I2C1_SDA]

      • Pin 13 [PA7]→ SCL2 [I2C3_SCL]

      • Pin 27 [PB4]→ SDA2 [I2C3_SDA]

    • Overcurrent GPIO pin connected to pin 9 [PA3] (regular I/O)

    • Everything else is the same as usual for the CAN adapter circuit except OSC_EN (connected to Pin 7, should be fine)