Links:

Design Notes/Justifications

Fan Candidates

https://www.amazon.com/Raspberry-Controllable-Control-Fan%EF%BC%8CRaspberry-40x40x10mm/dp/B0C4PN9BHK?source=ps-sl-shoppingads-lpcontext&ref_=fplfs&psc=1&smid=A5CVPLET1CA6

Best Fan Candidate

4 pins (5V, GND, PWM OUT, TACHO IN)

Claims 250mA max

https://www.amazon.com/Noctua-Cooling-Bearing-NF-A4X10-FLX-5V/dp/B00NEMGCIA/ref=d_pd_pss_dp_d_1_sccl_2_1/131-4794042-8775400?pd_rd_w=N46Zi&content-id=amzn1.sym.3dd6ff5f-e1b5-4c4b-9429-39c9f308776c&pf_rd_p=3dd6ff5f-e1b5-4c4b-9429-39c9f308776c&pf_rd_r=TGEQXVW5BY2A89NEMS3F&pd_rd_wg=fbnX7&pd_rd_r=19140b40-0674-4be5-ab82-24e65d06cee8&pd_rd_i=B00NEMGCIA&th=1

9 Pin Locking Connector

PCB connector

https://www.digikey.com/en/products/detail/molex/2023960907/7785664?s=N4IgjCBcoLQBxVAYygMwIYBsDOBTANCAPZQDaIAnAAxUD8ArgC4C2A%2BtkfQE5K4C81KiAC6AX1GEATGRCSqkgMwUAbFWoB2EaKA&utm_campaign=buynow&utm_medium=supplier

Wire connector

https://www.digikey.com/en/products/detail/molex/5013300900/1531506

Good stock (20,000+ on each item)
9 Pos
SMT, right angle mounted
Locking
Molex

LDO Selection

LDO is rated for 1A minimum and 1.3A typical? The 800mA is the current at which the dropout voltage is measured at, and for that there's a plot on page 8 of the datasheet that shows <1.4V dropout voltage at all temperatures at 1A output, so with a 5V input we should be in the clear. Based on that I'm going to leave the LDOs in, as even the minimum rating clears the absolute maximum of the ESPs

ESPs draw 500mA tops each

We should be in the clear with these 1.3A typical LDOs

Chip Antennas

Reference Designators

Mounting Grid

Board mounting holes are currently 90mm by 60mm which allows it to be mounted on a 30mmx30mm scheme that is standard in WARG. A future board revision may aim to move many components inwards and bring the board edge up to the connectors for aesthetic and board size optimization.

Via Sizing & Stitching

The following app note was referenced for stitching the GND pours around the RF sections: https://www.infineon.com/dgdl/Infineon-AN91445_Antenna_Design_and_RF_Layout_Guidelines-ApplicationNotes-v09_00-EN.pdf?fileId=8ac78c8c7cdc391c017d073e054f6227

Larger vias used for the stitching to provide more copper, providing better conduction capacity & continuity between planes (larger hole size = more copper around circumference of cut through plane)
Smaller vias used for signals and other areas to make it easier to fit vias closer together, i.e. for ESP signal fanout, due to large hole to hole clearance of 0.5mm required by JLCPCB
DECISION UPDATE: Learned that larger vias only provide marginally better current capacity. It is better to have more vias closer together (more vias actually provides more current capacity, closer together reduces inductance)
- For this board, larger vias will be replaced with the smaller vias to have all vias be the same size. Number of vias may be increased for certain power pours/ground stitching to improve current capacity & thermal performance. RF vias will be made smaller, but otherwise won’t be changed as spacing is already only 1/50th of 2.4GHz wavelength, much below the 1/20th maximum spacing recommended in Infineon app note linked above
- Discord conversation resulting in this decision: https://discord.com/channels/776618956638388305/1112251506339618836/1151579646274588742