Basics

There are no exceptions to the following rules.

• Every net in your schematics should be named with a net label

  • This is crucial as it provides clear information regarding the signal you are working with during PCB layout.

  • For example, it is unclear what kind of layout considerations are required for a signal named NetLabel_C15_1 (an example automatically assigned net name)

  • Power objects count as a subset of net labels as a power object assigned a net name in Altium

• net names should be all caps

• net names should not included spaces

  • Underscores are permissible

• Default Altium Color, font, and size should be used

• net names should appear horizontal in the schematic

  • improves readabilitiy significantly …

• net names should not have any non-underscore punctuation

Ground Nets

If you have just one ground, keep things simple, if you have more then net names should get more complicated/specific:

• GND

  • only use if you have a single ground on a schematic

• CGND

  • chassis ground, generally associated with mounting holes or ESD guard rings

• PGND

  • power ground

• AGND

  • analog ground

• VBATT_NEG

  • battery ground

Power Nets

Power nets must be defined such that their regulator topology and/or upstream source is clear. For example, the nets associated with a buck converter should have a prefix with “BUCK”.

For example, a +3.3V net and +12V net could be named PP3V3 and PP12V0 respectively. Where PP is short for Power Pole.

Power Rails

• PWR_3V3

• VBATT_48V

• VBUS_12V

Buck Converter Nets

For example, consider a 12V to 3V3 buck converter. The bootstrap net should be named:

• BUCK_PP3V3_BOOT

LDO Nets

For example, consider a 12V to 3V3 LDO. The feedback net should be named:

• LDO_PP3V3_FB

Digital Nets

GPIO Nets

For example, a 3.3 V LL (logic level) GPIO for commanding the select pin of a 2:1 multiplexer from an MCU should be named:

• GPIO_MCU_TO_MUX_SEL0_3V3

Generally,

• GPIO_A_TO_B_PURPOSE_LL

PWM Nets

For example, a 3V3 LL PWM for commanding the high-side FET of a half-bridge for phase U of a gate driver from an MCU should be named:

• PWM_MCU_TO_GDVR_UH_3V3

Generally,

• PWM_A_TO_B_PURPOSE_LL

UART Net

With A as the transmitter and B as the receiver, for 3.3 V Logic Level, we have:

• UART_A_TO_B_TX_3V3

• UART_B_TO_A_TX_3V3

Notice that both nets are defined to be transmitting. Tx and Rx are relative to the device so those terms are avoided to avoid ambiguity. The only difference is the direction from the transmitter and receiver. The “TX” can be omitted because it is implied. To understand how UART works refer to UART - Universal Asyncrohonus Transmitter Reciever .

SPI Net

With A as the master and B as a slave, for 3V3 LL, we have:

• SPI_A_TO_B_MISO_3V3

• SPI_A_TO_B_MOSI_3V3

• SPI_A_TO_B_CLK_3V3

• SPI_A_TO_B_CS_3V3

I2C Nets

With A as a master and B as a slave, for 3V3 LL, we have:

• I2C_A_TO_B_SDA_3V3

• I2C_A_TO_B_SCL_3V3

Differential Pairs

Consider a USB device

Analog Nets

Voltage Sense

Voltage sense analog nets should be denoted with a prefix “VSNS”.

• VSNS_A_TO_B_PURPOSE_LL

Current Sense

Current sense analog nets should be denoted with a prefix “ISNS”.

• ISNS_A_TO_B_PURPOSE_LL