Provided below is a list of commonly asked questions and corresponding answers regarding content present in the bootcamp. This document has also turned into a list of improvements EE leads should make when they have a chance.
Need to add section to component selection clarifying that chip resistors are most commonly used
Routing is unclear, make theory on routing
Ground planes need to be talked about more
Schematic and layout design should have a design rule checklist in confluence to help avoid confusion, there’s lot of common rules that newer members struggle with it seems.
Need to be explicit in defining input/output requirements to drive LDO IC selection.
The purpose of this document is to list and provide solutions to mistakes that leads hve noticed bootcampers frequently make. The goal is to codify these mistakes and how to fix them to make going through the bootcamp faster for prospective members and prevent leads from having to repeat themselves frequently.
Some relevant resources:
Schematic Symbol and Footprint Guidelines
Schematic
No four point nodes
Four point nodes, like the one shown below, should never exist in your schematic. The reason for this is only due to a flaw with Altium designer itself. Sometimes, when you have a 4 point node, Altium will not actually connect all 4 nets. It will connect 3 of them but not the 4th, but will still look like a compelte 4 point node. This can lead to significant issues down the line and if you don’t know what to look for it can be almost impossible to spot, as it will look the same as a properly connected 4 point node. For this reason we have a blanket ban on 4 point nodes in WARG.
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General cleanliness and legibility
An issue that we occasionally see with bootcamp schematics submitted to review is that they’re not very legible and do not look clean. The purpose of schematics is to show the connections between electrical components in a given electrical system; nothing more, and nothing less. For this reason, legibility is the top priority of a schematic besides having correct electrical connections. An example schematic is provided. You should not copy this schematic (it’s not even for an LDO!) but if you imitate its styling your schematic will look much better and you will probably go through the bootcamp faster.
Some common issues:
Inputs to the system start at the left, and move towards the output on the right, with whatever components they go through in the middle.
Nets are clearly labeled
Text does not overlap with other text or wires
Decoupling capacitors and any components connected to ground that are placed next to each other in the schematic should have their own individual ground symbols. This is one that you will sometimes see violated in industry. Not everyone agrees, but myself and WARG EE agrees that it simply enhances legibility and makes everything look better
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You need connectors!
This is one that I’ve seen a few times. The purpose of the LDO board you’re making is to take a given input voltage and provide an given output voltage. The input voltage needs to come from somewhere and the output voltage needs to go somewhere. This happens with the use of connectors. Connectors are used to physically attach external systems to your PCB, so you need one for the input and one for the output. You can kinda pick whatever one you want but ones frequently used in WARG PCBs are the JST-GH series and the XT series of connectors.
Layout
- Decoupling capacitors are placed as close as possible to the parts they are decoupling. If multiple caps are used, place them closest from smallest capacitance to largest capacitance
- All angles for traces and polygons are either horizontal, 45 degrees or perpendicular (no weird acute or obtuse angles - doesnt look clean and can cause fabrication issues depending on individual context)
- No polygons are shelved, and all are repoured
- No dead copper from any polygons
- Thermal reliefs are used where they are appropriate and not used where they aren’t. If you dont understand what thermal reliefs are for, Google it! (I’ve been asked this in a Tesla interview before btw, understanding what they’re for is actually good to know)
- No components underneath other components (check 3D body clearance in 3D view)
- No accidental antennas in the GND plane (bits of copper that stick out that arent connected anything - see below). Can be resolved by putting ground via(s) into the affected area or removing the antenna entirely. This one might be less clear so feel free to ask for clarification on what this is after doing some of your own research.
- Any 3-way intersections have traces perpendicular to each other. Do not have a trace that sticks out at an angle then becomes straight (see Figure 2)
- PCB has a ground plane - your board has more than one layer, so use that to your advantage! Have one layer that is entirely a ground polygon and connected to the top with vias. Lots of theory here so again, do some research and ask questions for anything that isnt clear!
- No angles < 45 degrees for polygons
- Traces are routed without acute angles
- Traces/polygons are appropriately sized for the amount of current
- Avoid overlapping polygons. Overlapping polygons of the same net should be merged into one