PCB Layout Review Checklists

Owned by Farris Matar
Last updated: 2023-08-18 by Zen Naseem
3 min read

This page is meant to provide a list of things that should be checked when reviewing the layout for a PCB. It is the designer’s responsibility to check for ALL of the things below themselves, then assign others to review their layout and ensure the changes required are made before sending the board off to be fabricated.

Specific Layout Sections for Review

Any significant circuits in your PCB should be reviewed individually to ensure the overall layout is OK and matches the manufacturer’s guidelines for the ICs. Create an Asana task for each of these sections and assign someone to review the section
Examples of circuits to go here would be: switching regulators, LDOs, microcontrollers, level shifters, translators, transceivers, etc.
Basically anything that has an IC, have someone review the layout of that circuit and make sure it fits with the layout recommendations in the IC’s datasheet. Ultimately, it is up to the designer’s discretion which specific sections need to be checked and what should be reviewed in those sections

General Layout Review Checklists

For each of the following checklists, create an Asana task and assign someone to review the ENTIRE layout adheres to the checklist.

Design-For-Manufacture (JLCPCB)

Ensures the PCB layout is in line with the capabilities of JLCPCB. If the board will be manufactured elsewhere, this section should be modified to fit the manufacturer’s capabilities. The capabilities of JLCPCB are listed here: https://jlcpcb.com/capabilities/Capabilities

When reviewing this section, instead of checking everywhere on the board, just make sure the design rules match what is on the manufacturer’s website, and the Design Rule Check reports no violations. Ensure the following sections are OK in the design rules:

Drill/hole size
Minimum annular ring
Minimum clearance
Minimum trace width and spacing
Solder mask

General Guidelines

General things to double check when reviewing the layout.

Decoupling capacitors are placed as close as possible to the parts they are decoupling. If multiple caps are used, place them closest from smallest capacitance to largest capacitance
No polygons are shelved, and all are repoured
No dead copper from any polygons
Thermal reliefs used for all parts, except for parts carrying high amounts of current - allows for easier rework
If possible, all 0805 components and smaller have copper balancing (copper connected to one pad is less than 2x the copper connected to the other pad) - this helps prevent tombstoning while soldering
No traces routed underneath inductors, unless it is on a different layer with a GND plane in between
Do not place small components (i.e. chip resistors/capacitors) next to very tall components (i.e. connectors) - make at least 1mm of space
Double check mounting holes are included if necessary (work with mech. team to determine if they are wanted)
No components underneath other components (check 3D body clearance in 3D view)
Ensure 0.5mm clearance from all mounting holes (set this up in your design rules)

Silkscreen

All silkscreen is TrueType Arial font, with a minimum text height of 50mil
Text block that includes the board name, revision, designer name(s), and completion date (month and year) is included on the silkscreen
WARG logo is included on the silkscreen
No vias over silkscreen
No silkscreen under components or over exposed copper (i.e. pads)
All components have their designators visible on the silkscreen
Check that all vias are tented

Routing & Pours

Avoid overlapping polygons. Overlapping polygons of the same net should be merged into one
No angles < 45 degrees for polygons
Traces are routed without any acute angles. Avoid 90 degree angles as well if possible
Differential signals are routed properly with length-matching
For signals with controlled impedance, trace width and spacing are calculated using Altium’s impedance control
When routing high-speed/differential signals between layers, surround the vias with GND vias

Connectors

Design-for-Test (Layout)