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Next, can let EFS team know of the design and to review that the PWM outputs from the ESP8285’s pins are possible and appropriate. Once that is complete, an EE lead can do a final review, and PCB layout can begin.

Input Filter Simulation

Mainly working off of https://drive.google.com/file/d/1S0Mzs7YdFf1vUP41wHp3JbctDb-8adoG/view, an impedance analysis plot across various frequencies was made to verify the function of the decoupling capacitor network. seeing as V/I = Z, the plot is labelled with V(v1)/I(V1). As equivalent series inductance and resistance values vary depending on frequency, many of the ESR/ESL values were taken at the 1MHz point of frequency (since the buck IC has a switching frequency of 1.2MHz), or taken from a general rule of thumb (I pulled these ESL values from Daniel’s presentation). Values from Murata SimSurfing.

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