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Overall Hardware Architecture (taken from https://uwarg-docs.atlassian.net/wiki/x/AoCsmQ )

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Info

The ports we are interested in:

  • PA9: SCL_1

  • PA10: SDA_1

  • PA7: SCL_2

  • PB4: SDA_4

  • PA12: CAN_TX

  • PA11: CAN_RX

Speculated ports:

  • PA3: Receives a digital signal representing whether an overcurrent occurred

  • PA5: Receives an analogue signal representing the cell voltages for cells 1-6

  • PB0: Receives an analogue signal representing the cell currents for cells 1-6

  • PB1: Receives an analogue signal representing the cell voltages for cells 7-12

  • PA2: Receives an analogue signal representing the cell currents for cells 7-12

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