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Table of Contents
stylenone

Introduction

WARG-Altium365 Link: https://warg.365.altium.com/designs/74D65A2E-05AC-4B8C-AE55-D8D307F760C7#design

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The only problem with this chip, is that the switching frequency is fixed, that may cause some problems when selecting Inductors, luckily, after calculation I can source pretty good inductors based on the fixed frequency, so in the end I chose the MP2491CGQB-Z chip

image-20240923-145338.pngimage-20240923-145409.png

EN Current Calculation:

R_Pullup +3kOhm (internal pullup) = (24V-7V)/I_EN (7Volt is the internal Zener Diode)

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In this case, R_Pullup=220kR, so I_EN=62.7uA, smaller than the 100uA, which is good.

Inductor

From the data sheet the design requirements of the inductors is that:

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For simplification I just used a 20uF capacitor (connected 2 10uF in parallel),

Output Capacitors:

The effective capacitance can be calculated as follows,

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To compensate the DC-bias and looking at the capacitors the WARG library already have, I selected 2 10uF capacitors with equivalent capacitance around 4.24uF at 5V DC and connect them in parallel.

Resistors

For the ILIM pin, a resistor is needed to set the current limit, according to the graph in the data sheet, to get a current limit of 6A we need 60.4kOhm resistor

For the FB pin, we need to build a voltage divider network to set the output voltage from the feedback voltage.

I have already set V_FB=0.5V by connecting VSEL_1 and VSEL_2 to VCC

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Updated (10/3): to compensate for the DCR losses, the voltage aimed to be regulated is changed to 5.1V

In this case, R1/R2=9.2, R2=10kOhms, R1=92kOhms, the library values I found are 10k and 91k.

System Block Diagram

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Reverse Polarity Protection

One feature of the buck converter that is nice to have is RPP. It can be implemented using the following methods:

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Overall, choosing a P-MOSFET and an IC are equally favorable, for the sake of learning I have chosen to use IC.

RPP IC selection:

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RPP diagram:

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PCB Layout

Some guidelines in the datasheet of the Buck IC:

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Placement

Initial placement:

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Kevin’s feedback are as follows:

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Some notes:

1. Top priority, input caps and output caps, Buck IC, and RPP circuit, then everything else;

2. the distance between the inductor and the switch node pin should be as close as possible;

3. the path for high current traces should be as large as possible (use polygon rather than traces for high current lines)

4. can move the RPP circuit down to leave more room for the BUCK IC

Updated Placements (From 9-30 to 10-2)

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Routing

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PDN Analysis

Goal is to calculate loop impedance for the following:

  • VBUS: Input connector -> NMOS, NMOS -> Buck IC

  • SW: Buck IC -> Inductor

  • 5V: Inductor -> Pixhawk Conn, Inductor -> USB-C Conn, also do Inductor to farthest decoupling cap down (basically before the via punch down to L4).

Used the Power Analyzer by Keysight tool, not able to calculate the loop impedance directly, use the voltage drop and current simulated to calculated loop impedance.

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image-20241025-165540.pngImage Addedimage-20241025-165417.pngImage Added

Pixhawk Wiring

The Pixhawk connector that I find is the 5024430670 Molex Clickmate connector, linked below:

https://www.digikey.ca/en/products/detail/molex/5024430670/2380429

The link below is the pixhawk wiring standard

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https://github.com/pixhawk/Pixhawk-Standards/blob/v6xupdate/DS-009%20Pixhawk%20Connector%20Standard.pdf

The wiring harness that WARG use is 1:1 harness, as pictured, the red cable indicating pin 1

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Comparing the cable with the pin placements on my PCB shows that it is correct

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