Change polygon property setting to “Pour Over All Same Net Objects”
Clean up polygons (just for my OCD, but it’s good practice!)
You can probably shift the IC and all the small components around it down and to the right (it will allow for GND to connect cleaner once you move the input and output decoupling capacitors around a bit)
For this, use a thicker trace (0.254mm to 0.381mm) to connect big VBAT polygon to the VIN pin
Make HO and SW traces as adjacent as possible
Consider rotating inductor to make current flow from SW to 5V as clean as possible
Increase trace sizes for HB, VCC, VCCX
Round the edges of the PCB with same curves as mine
Try to adjust input and output capacitors a bit more optimally
Move bulk capacitor closer to the board
Gap between RAMP and SS passives
EN resistor can be moved closer to IC
Make sure there is a cutout for the CSG current sense trace on the bottom layer as well (otherwise GND will connect to it, even though it is technically also ground)