Skip to end of metadata
Go to start of metadata

You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 36 Next »

Introduction

  • Who

  • Background

  • What

    • 30.5x30.5mm mounting pattern

    • 5V @ 4 A buck buck capability

    • high current pass through with 2x XT60s

      • 100 A pulsed current capability

      • 60 A max continuous current capability

    • pre accurate current sensing

    • Use the custom CAN circuit designed for ESC CAN Adapter .

      • EFS would need to dev for it but nws.

    • Single JST GH four pin to CAN x port on pixhawk

    • Balance Lead Connection

      • Measuring each cell voltage would be nice as well to improve SoC calculation.

      • would need 2x headers if we run two 6S batts in parallel which seems to be POR as of June 2024 for Fixed Wing 2025

    • Stretch requirement: Active balancing (Can be done, some extra circuitry required and must be taken into consideration in regards to component sourcing and which IC to use)

      • could be cool if there’s board space for it, hmm extra weight and risk tho, maybe not, EE lead thoughts

      • more work for firmware to develop cell balancing algorithm

      • save for next rev probably

    • Input Voltage Range: 26V to 12V

  • Target Use

  • Why

    • few COTS options with CAN

    • few COTS options with 30.5x30.5mm mounting pattern

    • Fun for EFS dev, opens doors for more complex SoC calculation

Electrical Architecture

Features:

  • Buck + LDO (Power Module)

  • Current Sense

  • Active Cell Balancing

  • Cell monitoring and measurement (SoC calculations)

  • MCU for custom cell balancing algorithm + cell input calculations + interfacing with IC

  • CAN circuitry

Elec System Design

Component Sourcing

Buck:

image-20240721-193004.png

  • Exposed Pad (Vin Exposed pad - pin number on symbol??? is this ok in general for a vin pin to be an exposed pad?)

  • What should I use for switching frequency? From what I’ve seen online, higher switching frequency means I can use smaller inductors and capacitors but increases losses.

    • Going to use 1M switching frequency for reduced board space. Seems to be a typo/mistake in the datasheet as the 5000 should actually be 55000 or 52500, so in theory RF should be around 47.5 to 50 kOhms. I will be using a 47k resistor because Digikey and Yageo do not offer a 46.6k

image-20240710-191337.pngimage-20240710-191457.png

  • Vout = 0.8 * (1 + R1/R2)

  • 5V output requires standard resistor values of: R1 = 52.3k, R2 = 10k (recommended from datasheet) this yields around 4.984V

  • alternatively, R1 = 53.6k yields around 5.088V

  • Even better, 10.5K, 2K gives exactly 5V (strange that this was not recommended by the D.S)

  • “The combination of R1 and R2 should be large enough to avoid drawing excessive current from the output, which will cause power loss” - This says nothing about the resistor values being too large so I will go ahead with larger values as it allows for a more accurate 5V rail

  • given this case: 105k and 20k would also be ideal

  • standard resistor values source: https://www.rfcafe.com/references/electrical/resistor-values.htm

Component Calculations

https://www.desmos.com/calculator/pn6h8na1mk

https://www.ti.com/lit/an/slva477b/slva477b.pdf?ts=1721655939318&ref_url=https%253A%252F%252Fwww.google.com%252F

image-20240721-202142.png

image-20240723-134722.png

Input Capacitor

  • Ideally <1% of Vin for ripple voltage so 0.01* (20V or 26V) ripple range: 0.2V to 0.26V

  • Cin should be between 3.75uF and 2.39uF, 3.3uF should be fine

image-20240723-142112.png

Output Capacitor

  • From online, it seems around 1% of Vout ripple voltage is desirable (lower is better obv)

  • Since we’re using X5R and X7R capacitors I’m assuming ESR can be ignored???

  • Vout is 5V so 1% is 0.05V would be preferred

  • For ripple current 0.2,0.3,0.4 of Iout = 4A (0.8A, 1.2A, 1.6A → 2uF, 3uF, 4uF)

  • higher capacitance = less ripple voltage = better 😄

  • https://rfcafe.com/references/electrical/capacitor-values.htm

    • Standard cap values within range: 2.2uF, 3.3uF

    • I will be choosing 3.3uF (at 0.3Iout ripple current, this is around 0.9% of output voltage (45mV)

    • Should be rated for >4A and >5V

image-20240723-134846.pngimage-20240723-134800.png

Inductor Selection (Section 3 of the TI document)

Others

  • Enable Pin is high between 1.2V and 5V so 3.3V from the AFE IC will be supplied to this pin (filter cap needed??)

  • Soft start Pin: “A soft start process begins when the input voltage rises to 3V and voltage on EN pin is HIGH. In soft start process, a 2.5µA internal current source charges the external capacitor at SS. As the SS capacitor is charged, the voltage at SS rises. The SS voltage clamps the reference voltage of the error amplifier, therefore output voltage rising time follows the SS pin voltage. With the slow ramping up output voltage, the inrush current can be prevented. Minimum external soft-start capacitor 850pF is required, and the corresponding soft-start time is about 200µs.”

    • will be using 10nF cap, was available on the WARG component library (relatively similar value)

  • Schottky Diode:

    • To reduce the losses due to the forward voltage drop and recovery of diode, Schottky diode is recommended to use. The maximum reverse voltage rating of the chosen Schottky diode should be greater than the maximum input voltage, and the current rating should be greater than the maximum load current.

    • Using the SK54A-LTP Diode which is already in the warg component library

    • rated for 40V @ 5A which should be enough for 26Vin and 4A current out

Cell Monitor IC

AFE Design:

  • image-20240719-134404.png Does D23 need to be implemented if we are using an XT90 Connector?

  • STM32

    • Using the STM32L431KCU6 (the same one from Meghan’s CAN adapter circuit)

Some thoughts:

  • Still not exactly sure how the cell monitoring should be handled, a BMS chip is kinda what I’m thinking or at least some sort of cell monitoring device. An issue I have right now is component sourcing since digikey’s search is yielding some fraudulent results (I think links 1 & 2 for the BMS) since most of the ones that say they can support up to 6 cells (from analog devices) really only support 2 Li-ion (I’m assuming this is the type of battery WARG uses).

  • The LT6810 chip seems really ideal but it operates SPI/I2C and is the master node in this case (is this alright?!?! I would expect this kind of peripheral to be the slave node in this case)

  • Most cell monitoring ICs are rated for more than 6 cells (usually 8-12) so I don’t think that is a huge problem that some pins won’t be used (redundant not optimal :0), almost none of them have a CAN bus serial protocol so I’ll need to use an IC to convert the signals most likely

  • Also, in a perfect world I would use the same IC to monitor current and cell voltage but most chips I have found only operate on one of the functionalities

  • Using two separate IC’s (one for BMS one for current), how does data transmission work if both are sending data on the line?

  • Optimal IC I think would be the BQ7692, might be wrong here but I think it has current sense capabilities

  • No labels