Status: Active

Current Owner: Jerry Tian

Previous Owner: Stanley Hao

Needs Assessment

The 12S Servo Module is a PDB designed to supply power from the battery directly to the servo motors on the fixed wing plane. The board should step down the voltage from the battery to 5-6V to supply the servo motors and be able to cut one out if it fails, to prevent the dead servo from drawing too much power and depowering other components of the drone.

Market Research

• Existing https://www.revrobotics.com/rev-11-1144/, interesting LED feature can be implemented.

  

  • see if we can get plane position from gyro?? is a gyro chip too big?

  • or I need to study how to read fixed wing directions from its wing tilt angle?? and we can get this data from servo?? but how to decode!???

  • or simply we just measure current at each servo rail input and mux the color ?? uhh so many ideas I am not even sure if they make sense lol

• I (Jerry) assumed 1 servo motor draw a maximum of 1A from my previous course project. I saw 1 servo motor would draw around 700mA from power supply. Also saw a bunch of servos in the bay and they look the same size as the one I used in the course project, so I assumed 1A current limit.

Requirements

• Supports 18 V to 55 V input from XT60 for 6S and 12S support

  • Input should have common mode choke to filter out noise from the ESC

• 3x4 header servo inputs and outputs to be consistent with Pixhawk Electrical Connector Standards

  • .100 pitch, 100mil

  • Input: PWM, GND from Pixhawk (No 5V power since we are making our own)

  • Output: buffed PWM, Power, GND

• Each output power is 6 V (possibly adjustable between 5 V and 6 V with passive values) and has a current limit somewhere between 500mA and 1A (possibly adjustable with passive values within this range). If one channel is over currented the other channels remain alive.

  • 5V/6V output can be changed by swapping out resistors

• 30mm x 30mm PCB size to be compliant with Mounting Hole Specifications

Block Diagram

Possible Implementation Methods

Single Buck Converter Option

• A single buck converter with external FETs can be used and then four current limited channels

  • Will need to have the current limit max at 4A

  • Each servo line will have some form of overcurrent protection, which can shut off that line to the servo if the current exceeds a certain limit

4 Buck Converters Option

• Four separate buck converters with internal FETs can be used, each with their own current limit

• Adding fuses to each servo line that will trip if the current exceeds allowed parameters?

Methods Pros and Cons

Decision: We selected single buck option to save board space.

Component Selection

Buck ICs

Internal FETs

• LM76005 3.5-V to 60-V, 5-A Synchronous Step-Down Voltage Regulator datasheet (Rev. A) (ti.com) (Thanks Steven)

  • For single buck option

External FETs (Buck Controllers for single buck option)

• MP9928 Monolithic Power

  • Readily available on Digikey, lower efficiency than the Ti ones (high 80’s at nominal)

  • Reference Design: rd00002_48v_mpq2908_reference_design_rev1.0.pdf (monolithicpower.com)

MP9928 Buck Controller Specs

Typical Application Circuit Diagram

IC Pinout

• This IC is available in TSSOP-20 and QFN-20 packages.

Important Equations

• Output voltage divider equation:

  

Buck Controller Passive Components Selection

Output Feedback Voltage Divider

• For 6V output, use 130k & 20k 1%, currently using this

  • R8 = 130k → RC0603FR-07130KL YAGEO | Resistors | DigiKey

  • R9 = 20k → RC0603FR-0720KL YAGEO | Resistors | DigiKey

• For 5V output, use 43k & 8.2k.

  • R8 = 43k → RC0603JR-0743KL YAGEO | Resistors | DigiKey

  • R9 = 8.2k → RC0603FR-078K2L YAGEO | Resistors | DigiKey

V_out Current Limit

Since we have overcurrent protection downstream already, we don’t want to implement a limit on the buck controller itself. Unfortunately, the current sensing is used in the compensation control for the buck, so it needs to be included for the IC to function normally.

• Rearranging the inductor equation from Inductor Selection below, Ipp-ripple = 1.149A, then Ipk = 4.5745A, therefore, a current limit of 5A should suffice.

• Assuming ILIM pin is GND, V_ILIM = 25mV

• Rsense = 25mV/5A = 5E-3Ohms = 5mOhms

• Expected power dissipation: P=I^2R, P=5^2 * 5mOhms = 0.125W

• 5mOhms current sense resistor: https://www.digikey.ca/en/products/detail/rohm-semiconductor/PMR18EZPFU5L00/2094203

V_cc Circuit

The MP9926 has VCC1 and VCC2 to power internal components and the MOSFETS. VCC1 can take input from Vin into an internal LDO. To improve efficiency, can connect VCC2 to output and leave VCC1 pin floating.

• Choose a 4.7 uF capacitor for VCC2

  • 4.7uF is chosen to be compliant with datasheet’s typical application example. This cap decouples noise at VCC2 pin. Other values such as 1uF or 10uF would work as well.

• Choose 1uF capacitor for VCC1 according to the datasheet

  • VCC1 cap can’t be drained when charging up the bootstrap capacitor, the 1uF cap is chosen since it is 10x bigger than Cboot

Power Good Pull-up Resistor

• PG pin not required in implementation, DNP resistor provided as shown. 100k resistor used in earlier design shown below.

  • https://www.digikey.ca/en/products/detail/yageo/RC0603FR-07100KL/726889?s=N4IgTCBcDaIEoGEAMA2JBmAYnAtEg7AIxJIDSAMiALoC%2BQA

Enable/Sync Pin Pull-up Resistor

• selected a resistor divider here to regulate EN pin voltage in high Vin situations

  • 1.28V < V_EN < 50V

  • Vin = 18V, R1 = 100kohm, R2 = 100kohm, Vout = 9V

  • Vin = 55V, R1 = 100kohm, R2 = 100kohm, Vout = 27.5V

• not using a zener diode because the diode footprint takes too much space

AAM/CCM Resistor

• AAM mode improves the efficiency of the the Buck at light or no load, and since we are powered by a battery, it would make sense to improve the efficiency of the board where possible.

• Choose 196K resistor, this keeps the V_AAM at 600mV which is above the 480mV (R_FREQ is also 200K so the resistors cancel out which leaves V_AAM at 600mV).

Soft-Start Capacitor

• Soft-start capacitor is used to determine the soft-start time, prevents converter output voltage from overshooting rated voltages

• 

• If we want a t_ss of ~100ms, I_ss = 4 uA, V_REF = 0.8V, C_ss = 500nF

  • Easier to find caps with 0.68uF capacity, resulting inh t_ss=136ms, which should still be fine for our purposes

  • https://www.digikey.ca/en/products/detail/yageo/CC0603KRX7R8BB684/16797741

    • CAP CER 0.68UF 25V X7R 0603

  • Justification: We don’t need soft start time to be very fast, having slightly longer gets us less inrush current.

Switching Frequency

There is a trade-off when selecting the switching frequency of the buck controller.

High Fsw → Small input and output ripples, smaller inductor and less capacitors but will increase switching losses

Low Fsw → Big inductor but small switching losses

• Limits: 100kHz - 1000kHz

• Try to use lowest available frequency (100kHz)

  • Justification (Old): Even with the lowest available frequency available to us, the corresponding recommended inductor size that this corresponds to is just 47uH which isn’t too physically large anyway, and we aren’t very space constrained so larger a couple larger components is okay, thus to maximize efficiency, we can go for the lowest possible switching frequency.

  • Justification: 100kHz switching frequency provides the highest efficiency. It leads to a 47uH inductor which is fitting our 30mm x 30mm board so this switching frequency is acceptable.

• 

• 199kOhms → selected R_freq = 196kOhm → Fsw = 101.5 kHz

• Comment:

  • If we ever go for a 2nd revision, start with calculating total losses on the FET and go for the highest Fsw. We want the board size to be small so a smaller inductor and less caps can help with layout. But still watch out for efficiency drops

Inductor

• SRP1265A-470M Bourns Inc. | Inductors, Coils, Chokes | DigiKey → 47uH, 6.5A, 90mOhms

• Rated DC current is recommended to be 25% higher than typical for safety.

• Inductor size equation from datasheet:

• V_out = 6V, V_in = 55V, f_s = 101.5kHz, i_ripple = 0.3 * 4A = 1.2A: L = 43.9uH

• V_out = 6V, V_in = 18V, f_s = 101.5kHz, i_ripple = 1.2A: L = 32.8uH

• At 4A, the inductance drops a little from rated 47uH but is still close to 45uH, also the expected temperature remains low, thus this inductor should be sufficient

Input Capacitor

When the switching FETs turn on and off, current suddenly start and stop flowing and this causes ripple on the input side. Due to the parasitic inductance, we see the ripple voltage on Vin and we need to filter that out.

• Must be capable of handling input ripple current, some power will be dissipated by the capacitor ESR. Typically quoted values of ESR for ceramic capacitors are between 0.01 and 0.1 Ω. The ripple current can be defined as follows:

• 

  1.25A@V_in=55V, 1.89A@V_in=18V

• Voltage rating ideally greater than 100V to compensate capacitor DC bias effect

• Below: Input capacitance equations from TI appnote:

• See efficiency chart below for duty cycle calculation

  

  • @V_in = 55V: D = 6/(55*0.85) = 12.8%

  • @V_in = 44.4V: D = 6/(44.4*0.85) = 15.9%

  • @V_in = 22.2V: D = 6/(22.2*0.92) = 29.4%

  • @V_in = 18V: D = 6/(18*0.92) = 36.2%

• f_sw = 101.5kHz, I_o = 4A

• To save board space, we decided to go with ceramic capacitor only. Chosen 4 10uF 100V X7S ceramic capacitors as our input capacitors. See the screenshot below for DC bias and Temp Rise due to I_rms.

  

• Let Vpp be 2% of Vin, this would yield a Vin_max of 55.55V. There is still 4.5V margin till the Vds_max for our switching FET.

  • Cin @ 55V >= 0.128 * (1 - 0.128) * 4 / (1.1* 0.1015) = 3.86 uF, effective capacitance = 2.22*4 = 8.88uF > 3.86 uF

  • Cin @ 44.4V >= 0.159 * (1 - 0.159) * 4 / (0.888* 0.1015) = 5.74 uF, effective capacitance = 2.9*4= 11.6uF > 5.74 uF

  • Cin @ 22.2V >= 0.294 * (1 - 0.294) * 4 / (0.444* 0.1015) = 17.81 uF, effective capacitance = 5.84*4= 23.36uF > 17.81uF

  • Cin @ 18V >= 0.362 * (1 - 0.362) * 4 / (0.36* 0.1015) = 24.44 uF, effective capacitance = 6.69*4 = 26.76uF > 24.44 uF

Added one 0603 0.1uF cap at the buck controller input to match the datasheet guide.

Conclusion: We can go with ceramic capacitors only for our design. Vpp_max is 1.1V, which can cause problems at the SW node if the noise frequency matches the converter’s resonance frequency. However, we also have boot resistor, snubber circuit and gate resistor to suppress the SW node ringing.

Comparing Different Capacitor Options

Selection: Al Polymer 160V CAP ALUM POLY 10UF 20% 160V T/H

Justification:

• Rated for 160V which should provide ample safety room to the rated 60V design voltage for the board

• Quite affordable compared to using just ceramic capacitors

• Space efficient, requires only one to provide adequate capacitance

• Low ESR, at 110mOhms tested at 100kHz compared to regular electrolytic capacitors

• Through-hole makes it easier to solder(?)

Small input ceramic capacitor to handle input spikes and phase-node ringing

• CAP CER 1UF 250V X7R 2220

Output Capacitor Selection

• Cap impedance should be low at switching frequency (101.5kHz) as the inductor current oscillates at this frequency.

• Datasheet uses 22uF and 220uF capacitors for 5V application

• 22uF: GRM21BR61E226ME44K

• Keep output ripple voltage to a minimum

• Vout = 6V

• Vin = 55V

• f_s = 101.5kHz

• L = 47uH

• R_ESR = 0.004R / 3

• Co = 8.192uF * 3

• Delta V_out = 0.0562V if put three 22uF capacitors, very quiet Vout, very nice

Compensation Components

• Assuming we did have a R_sense resistor of 5 mOhms:

  • 

    Gm = 500uA/V

  • Gcs = 1/(12*Rsense) = 16.67

  • Co = 8uF * 3

  • fc = 0.1 * fsw = 10.15kHz

  • Vfb = 0.8V

  • R5 = 1357 Ohms → 1300 Ohms

  • C6 > 49nF → C6 = 100nF

  • C7 = DNP for tuning.

RC Snubber

Purpose: reduces the voltage ringing spike at SW node

How it works:

The PCB trace parasitic inductance and LS FET output capacitance (Coss) forms an LC circuit. The SW node is right in the middle of L and C so it will see a lot of voltage ringing. The snubber circuit serves as a low impedance path for the high frequency voltage oscillations similar to a 1st order RC low pass filter. Half of the energy will be dissipated through R_snb while HS FET is conducting and the other half will be stored in C_snb. While LS FET is conducting, current will flow out of C_snb and dissipates energy through R_snb again.

Do we need it?

• We don't want a transient to damage the switching FET

• DNP the snubber the circuit for the 1st revision, we will find out if we need them during testing

Research Links:

• Determine R and C values in the RC snubber design

• RC Snubber circuit explanation and Snubber Circuit Calculation

Power FET Selection

MOSFET basics: an-1084p1.p65 (infineon.com)

Requirements

• Vds > 55V max?

• Ids > 5A (Id_min = 4.5745A)

• lower Rds the better

• Small size → son-8 package

Decision Matrix

• MOSFET &#8212; Power, Single, N-Channel 60 V, 6.1 m&#937;, 71 A (onsemi.com)

  • Overkill, too big

• DMN10H170SK3-13 Diodes Incorporated | Discrete Semiconductor Products | DigiKey

  • Vds = 100V

  • Ids = 12A

  • Rds = ~150mOhms

Total Switching Loss =  Gate Charge switching loss + Output Capacitance switching loss = 1/2 * Qg * Vgs * fsw + 1/2 * Coss* Vds^2 * fsw

Decision: we choose Diodes Incorporated DMTH6016LK3-13 as our buck converter’s switching FETs.

Decision: Selected Texas Instrument CSD18534Q5A as the switching FET for low cost, small package and small losses.

Bootstrap Circuit

Purpose: generate bias to drive the gate of the High Side FET

How it works:

1. When SW node is GND, internal 5V VCC charges up Cboot through forward biased diode

2. When SW node is Vin, Cboot still maintains that 5-Vf voltage since the charges on the capacitor has nowhere to go and V = Q/C. The schottky diode blocks current from flowing back to the voltage source.

High side switching FET gate capacitance: Cg = Qg / (VCC1 - V_bootDiode)

Cg = 11.1 nC / (5 V - 0.45 V) = 2.440 nF

Cboot > 10 * Cg

0.1 uF >> 0.0244 uF

Conclusion: Using a 0.1 uF capacitor for Cboot will work. DC derating must not lower the capacitance at 5V.

Two resistors can be placed in the bootstrap circuit for tuning.

1. Rboot: Placed in series between Cboot and the diode to limit the charging inrush current to the bootstrap capacitor.

Iboot = Cboot * Vboot / charging time = Cboot * (VCC - Vf) / (1/fsw*(1-DutyCycleMax)) = 0.1 * (5-0.45) / 1/100k*(1-0.362) = 71.32mA

Conclusion: we don’t need a inrush limiting resistor.

2. Rbst: Placed in series between Cboot and the BST pin to slow down the rise time of the HS FET. Note that a large value on this resistor will trigger the UVLO on the HS gate driver.

This resistor is also helpful to reduce the ringing effect on the SW node by slowing the rise time. It is the most efficient method as the gate resistor and snubber circuit dissipate energy when the HS FET is turning off while Rbst does not do that!!

Diode selection:

This diode needs to recover fast to block charges on the SW node when HS FET is conducting. And also need to have low Vf to charge Cboot.

Vr > Vin - VCC1 = 50V

Io = Iboot = 71.32mA

selected https://www.digikey.ca/en/products/detail/diodes-incorporated/DFLS160-7/765614

Common Mode Choke

Needs Assessment

Why do we need this filter?

The common mode choke serves as a protective measure against potential ESC and environmental EMI common mode noises. Typically, it functions as a short, connecting the battery and the buck converter input. The power FETs of the ESC constantly alternate between the battery's power and ground, causing ringing at both VBAT and ground, known as common mode noise. Since the servo module draws power from the same battery, the noise has the potential to be transferred to the buck converter's input. Ideally, the ESC addresses its FET ringing issue on the PCB. We added common mode choke for an extra layer of noise mitigation.

How does the common mode choke work?

This noise, known as the common mode noise, will affect both power and ground rails. To maintain the voltage at our buck converter’s input, we use a common mode choke chip to attenuate the common mode noise.

When differential currents are coming through, the magnetic field substracts so currents pass through without any impedance. When common mode noise are coming through, the magnetic field adds so the noise current will experience a lot more impedance and most of the noise will be blocked at the choke.

Research Notes:

https://electronics.stackexchange.com/questions/630389/why-does-the-signal-and-power-supply-in-my-custom-esc-breadboard-become-so-noisy

A Survey of Common-Mode Noise

https://electronics.stackexchange.com/questions/79752/what-is-common-mode-noise

https://electronics.stackexchange.com/questions/320733/what-exactly-happens-to-the-signals-hitting-a-common-mode-choke

Requirements

• Current rating > 4.7A

• Voltage rating > 55V

• Filter capabilities has little impact because we need fit this big chip on our tiny board

Options

• ACM7060-301-2PL-TL01 TDK Corporation | Filters | DigiKey

Efuse Component Selection

Efuse IC Selection

The table below shows some overcurrent IC options I have found:

• Adjustable Current Limit of Smart Power Switches (Rev. B) (ti.com)

  • This series of TI chips can only run a max input voltage of 40V, we can put them after the buck and it be okay

  • TPS1H000-Q1 40-V, 1-Ω, Single-Channel Smart High-Side Switch datasheet (Rev. C) (ti.com)

    • Can externally set current limit from 50mA to 1A

      • Can be set using a resistor at the CL pin to GND, value is set using the following equation:

        

      • R_CL is the resistor

      • Where V_CL(th) is internal band-gap voltage (0.8V for this IC)

      • K_(CL) is the ratio between output current and the set current limit value

      • I_OUT is the output current

    • 3 Modes of operation when device is tripped:

      • 

    • Auto-retry probably the one we want to go for as it can retry letting current through at intervals

      • Could just pullup delay input to Vs

    • Can be controlled by a MCU and work standalone

      • 

      • Could maybe even add some breakout connections for DIAG_EN and FAULT if in the future we want to had diagnostics with a microcontroller

• MAX17613A/MAX17613B/MAX17613C - 4.5V to 60V, 3A Current-Limiter with OV, UV and Reverse Protection (analog.com)

  • This might also work…

• XC8108.pdf (torexsemi.com) (has max voltage of 5.5V)

Selected Efuse IC: TCKE8xx Series

The auto-retry version was chosen so that each servo will continue to attempt working while we are in the air and so that we don’t lock out a servo mid-flight.

Input and Output Capacitor

https://www.digikey.ca/en/products/detail/samsung-electro-mechanics/CL10B104KA8NNNC/3886664

Also, assuming a 2.6ms rise time, and a very low resistance on the line, two 1uF for the input capacitor should be enough to allow the voltage output to rise in 2.6ms from 0V to 6V.

Current Limit Resistor

R_ILIM = 117kΩ if I_ILIM is set to 1A

https://www.digikey.ca/en/products/detail/yageo/RT0603DRE07117KL/7708397

Slew Rate Control Capacitor

Use 1nF capacitor from altium library.

This results in a t = 2.6ms rise time for 6V output.

Input Zener Diode

The zener diode protects the chip from inductive voltage spikes from sudden current increases. Think of V = L * di/dt but di/dt is infinity.

Calculation of input voltage spike from the datasheet:

Assuming perfect conductors on the input rail, this formula is a simple ohm’s law where the R becomes the characteristic impedance of the input rail, which is sqrt(L/C)

Lin = 47 uH (buck inductor)

Cin = buck input caps + buck output caps + 4 current limit ic input caps = 10uF*2 + 22uF*3 + 1uF*8 = 94uF

Vin = 6V (worst case)

Iout = 1A

Vspike = 6.707V which is less than the 18V absolute maximum input voltage.

Conclusion: we don’t need a zener diode at input.

Output Schottky Barrier Diode

This optional SBD on the output of the Overcurrent IC may be needed such that no instant changes of the voltage to the motor/servo or when the current suddenly shuts off to 0A creates a negative voltage spike (although ideally servo has flyback internally to deal with this)

The SBD will clamp the output voltage at -0.28V for chip protection since the datasheet specified the absolute minimum Vout is -0.3V. It will be placed for the 1st revision just in case if things go wrong.

PWM Buffer Component Selection

Servo Motor Market Research

Most servos can handle 3.3V & 5V logic levels but some high torque servos only take 5V logic level and doesn’t respond to 3.3V PWM signals. Therefore we want to buff the 3.3V PWM signal coming from the flight controller (Pixhawk 6) to 5V.

Google search “step down servo motor PWM signal from 5V to 3.3V” gives guides on the opposite… so we don’t need to worry about 5V PWM not compatible. Plus we have jumpers to get around the buffer if we really want a 3.3V PWM signal.

Requirement

• 4-channel

• 5V Vcc

• Level shift PWM signal voltage from 3.3V to 5V https://docs.holybro.com/autopilot/pixhawk-baseboards/pixhawk-baseboard-ports

Selected SN74AHCT126PWR for cheap price and small package.

3.3V buffer backup: SN74HC125PWR

5V LDO

Current consumption of the buffer is 25mA max, Vdrop = 6V- 5V = 1V, Ploss = 25mW worst case. No need for a big package to dissipate heat. Selected AP7375-50SA-7 for cheap price, small package and VDROP = 350mV @ IOUT = 100mA (Typ.).

3.3V LDO backup: AP7375-33SA-7

Input Pulldown/Pullup Resistors

I couldn’t find Pixhawk PWM rail leakage current. Assuming 100uA leakage current from Pixhawk and open drain configuration, 4.7k pulldown will create a 0.47V input, which is below the 0.8V logic low threshold. 4.7k pullup will create a 0.47V drop, which would still above the 0.7 * Vcc threshold at 3.3V Vcc.

Selected 4.7k as pulldown/pullup resistor value.

PCB Layout Notes

Layout Topology

• XT60 connector comes in at the middle-left of the PCB, following by the common mode choke

• HS FET on the right then LS FET next to it, inductor is placed under the FETs

• All buck controller components stay on top layer, except for jumpers, they can be anywhere

• 4-channel buffer on the top of the bottom layer, then the Efuse ICs

• Mounting holes at 4 corners, no extra space beyond them

Layout Justifications

Trace Width Calculations

I assumed the board can handle 20C temperature rise just from air cooling. Source: Saturn PCB

For 1A traces in and out of the efuse IC, I’m using trace width >10mil

For 4.57A traces in and out of the buck, I’m using trace width >50mil

Via Current Calculation

Via Size

Via hole: 0.15mm

Minimum Annular ring: 0.13mm

Via diameter: 0.15 + 0.13*2 = 0.41mm

This setting is chosen so that the board uses the smallest via size possible while not paying JLCPCB extra. 0.15/0.41 size vias also makes it easier to terminate ground copper dead ends. Though some cases we can use a larger via (e.g. 0.3/0.6), it increases drill sizes and increase manufacturing cost.

Layer Stackup

Copied JLCPCB 4-layer stackup since I want internal ground layers to be as close to the top and bottom layers as possible. Reason being I want the ground plane to absorb as much noise as possible on the top and bottom layers, especially the magnetic field from the inductor.

Efuse IC Pad

Removed vias on the ground pad of efuse IC, so everything can fit on a 30x30 mounting hole pattern. Justification:
Maximum power dissipation would be 1A*1A*38mohm = 38mW.

Assuming a 50 C/W thermal resistance, temperature rise is only 1.9 C.

Input & Output Connectors

Input connector and output connector both follow the pixhawk flight controller PWM connector 3x4 pattern. Top row is ground, mid row is power and bottom row is signal.

Online 3D body for the input & output header in the PCB file is wrong so it is removed from the layout. The correct mating length is 5.84 mm which matches PWM cables.

As of 2023-11-19, 12-position-3-row female sockets are out of stock, link to its datasheet: https://suddendocs.samtec.com/catalog_english/ssq_th.pdf

Alternative is to use two 6-position-3-row sockets together if the above remains out of stock

BOM notes

1. Add 2.2 ohm resistor for bootstrap tuning

2. Order 4.7k resistor for buffer input pullup/pulldown