Weekly Summary - Kenny Na

Owned by Daniel Puratich
Last updated: about 5 hours ago by Kenny Na
4 min read

Introduction

Brief documentation of what Kenny Na’s been up to each week to help in synthesis of final report and so @Daniel Puratich can visualize where the time is going and help resolve roadblocks. Formatting is expected to be similar to Weekly Summary - Meghan Dang .

Table of Contents

Related Resources

Weeks

Week 1

  • Started and finished WARG Electrical Bootcamp

    • Selected an IC and connectors from DigiKey and incorporated Bootcamp library

    • Created footprint for the regulator IC from scratch and imported 3D model

    • Created a schematic and PCB layout for the LDO regulator device

  • Beginning to build a conceptual and more scientific understanding of electronics and power through lectures from Daniel and Kevin, as well as online resources in Confluence, etc.

    • Parallel & series, resistors, (decoupling) capacitors, inductors, DC and AC, operational amplifiers

  • Received new material in advance for the next project: developing a buck converter for the fixed-wing aircraft

Week 2

Week 3

  • Finished the schematic capture for the 12V-5V @ 4A Buck + ELRS TX project

    • Connected data lines between MCU and RF IC

    • refined resistor and capacitor selections, added a bulk capacitor

    • Added net labels to each of the nets in order to make future PCB layout easier

    • Finished adding the connectors, with 2x XT60-PW-F @ 12V for the motors and 6x GND, 5V, and PWM for servos

    • Needs some final edits to the styling and a schematic review from EFS team to make sure the pinout is correct/possible

  • Working on simulating the input filter (decoupling capacitor network) for the buck converter in LTspice

Modelling V/I (impedance of the overall circuit) in LTspice. Creating a capacitor simulation with ESR and ESL. Pulling data from Murata SimSurfing.

  • Beginning PCB layout for the project.

    • Defining physical board requirements - 30.5x61mm, 4 layer, single-sided (for ease of design? mounting? I mean you could use standoffs)

Week 4

  • Final edits to the schematic made, started adding notes to the page so design decisions are easily explained, reviewed specs one more time

    • sorted out the connectors through GPIO 0/2/15 and U0R for EFS team

  • Finished work on the input filter simulation - frequency domain and time domain

    • Thinking about system level simulation, all of the factors of impedance throughout the circuit

    • Found the 22uF cap was (1) not enough for the current power requirements and (2) didn’t even have any ESR/ESL numbers in the datasheet, so we switched to 47uF bulk cap

LTspice simulation in frequency domain

  • Finished 4 tries of buck converter component layout

    • 30.5x60.5mm initially, and then 30.5x30.5mm worked so we switched to that

    • system-level thinking: placing 1x3 connectors next to the XT60-F since they will go across the sides of the fixed wing plane

Week 5

  • Have done a total of 9 tries at layout now, landed on a final working design

  • This one has an efficient placement of the buck converter, good placements of header pins, connectors were moved to the back of the board (as well as the feedback loop for the buck), the ESP antenna at a board edge, RF antenna placed nice and close to the SX1281 RF IC, nice large polygon pours for the 12V/5V/3V3 power runs

  • Minor schematic changes for readability

  • Participated in board bring-up and used solder paste + stencil for SMT soldering

  • Rewrote the WARG EE onboarding from memory for fun

Week 6

  • Utilized SaturnPCB software to find appropriate trace width for impedance matching at 50 ohms

  • Finished the final revision of the PCB layout. Made many edits and simplifications to schematic

  • Reviewed datasheet for buck, increased FB resistor values (doubled), ended up leaving calculated Vout value at 5.1V.

  • Watching TI layout recommendations.

  • Started learning about USB-C PD protocol and new project: USB-C Sink

Week 7

  • Just kidding on completing 12V -> 5V @ 4A Buck Converter + ELRS Board

    • Review on ExpressLRS Discord prompted an MCU change to the ESP32-C3

    • Stronger PWM signalling than 8285 and active support for new ELRS hardware targets

    • Added new parts and read through Expressif’s Hardware Design Guidelines for ESP32-C3

      • Decoupling capacitor selection for external crystal, inductors in series, matching network

    • Redid the entire microcontroller schematic and layout…

  • Researched 4 USB-C PD IC options for USB-C Sink project.

    • Created a decision matrix to narrow down what chip to use.

Week 8

  • Started and finished schematic for USB-C Sink project.

    • Researched general USB-PD controller behaviour, gate/FET behaviour, PD arbitration

    • Read the TPS25730 datasheet and found a >100uF bulk capacitance on the VBUS/PPHV line can cause inrush current spikes during initial connection of power to the sink device

      • Went down a rabbit hole of USB-PD specification and USB 3.2 inrush current requirements

      • Found out the TPS25730x handles inrush current limiting by itself by employing a Slow Start (SS) behaviour of slew rate limiting and external gate control (and trying to confirm this with TI rep)

      • Learned about the concept of open drain output from a FET.

        • Drain pin and pads on the PMIC.

  • Began to understand I2C protocol from an electrical level

    • I2C has data line and clock line, where the data is synchronized with the clock.

    • I2C bus is a form of an “open drain output”, where the bus is either left floating (High-Z, or High Impedance), or pulled to ground using a FET internal to the IC.

      • Open drain outputs must be pulled high externally to enable use of the line (floating potential is too low for a a slave/master to switch to ground and have that pull down be readable by anything on the bus)

      • The value of the pull-up resistor used to enable communications on the I2C bus is variable, and depends on the total capacitance of the bus and the frequency the bus needs to operate at.

        • This is because naturally, a lower resistance will charge/discharge the capacitance of the cable/connector quicker, giving a cleaner, steeper edge during pull-down sequences.

        • It makes sense that lower-frequency I2C transmission would have more relaxed resistor value requirements, allowing slower rising edges and (therefore) higher resistor values.

    • Master and slave are connected on the bus, generally only one master (more is complicated)

      • Only the master can initiate and end data transmission using a start/stop sequence

      • The slave will send its address with 7 bytes (127 addresses), one read or write bit, and then an acknowledge (ACK) bit to confirm viability of the data transfer

Week 9

  • Started and finished PCB design for USB-C Sink project.

    • A few layout passes, some changes to stackup (4-layer due to controlling impedance)

    • Schematic changes to adjust LED behaviour/brightness, and input/output capacitors

      • Good to check the IC EVM and see what kind of capacitance you can get away with

    • 2 passes at routing to get it right, CC pins impedance matched to 50 ohms and avoiding plane splits (more justification in the project documentation)

    • Very nice silkscreen this time, improving the PCB aesthetics (meaningless lol)

      • Adding labelling for ease of use, as well as I2C programming pads, being aware of how the device is going to be used while implementing features

    • Generally thinking/watching more content about how to route high-speed signals in PCBs

    • Improving the conciseness and clarity in my project documentation

  • ValidatedSingle Servo Driver buck functionality using the Single Servo Driver Test Plan

    • Daniel explained how to effectively use the benchtop DMM and power supply

      • with DMM, ground and test for shorts on data pins or for low resistance on power rails.

        • power rails will have high resistance to ground as the return path varies.

      • powering the buck on Single Servo Driver with power supply, pretty straightforward stuff I guess I was afraid of blowing shit up before

        • slowing cranking it to 30V at 0.1A then testing output for 5.7V, beautiful when it works

      • Nothing with oscilloscope or eload yet, neither did I do any efficiency testing (sad, gg)

  • Attended the 2024-11-02 Competition Flight Test, observing and helping with comp drone prep happening in the bay throughout the week and helping with calibration for Pegasus 2 on site

    • Created 4-pin CAN harness for the LEDs connecting to the Pixhawk on Peggy

      • Cool standardization documentation for Pixhawk standard

    • Created 5-pin JST/CAN to 2.54mm pitch receptacle headers

      • Holy shit I suck at soldering

  • Attended Jerry Tian’s Validation Presentation

    • Was barely awake for this one unfortunately, however a lot of interesting concepts were discussed

    • 4 wire testing

    • concept of e load

    • step-based efficiency validation and linear efficiency validation

  • Briefly revisited buck converter/switching mode power supply fundamentals, component features

    • Daniel showed discontinuous conduction mode on a synchronous buck converter on whiteboard

      • Forced PWM mode: switching is “continuous”(???) but is specified as a type of discontinuous conduction mode formally, lets the inductor output current go negative (???) (reverses current flow?)

      • Diode emulation mode: stops current from flowing negative (backwards), IC will turn output off when current hits 0 (near 0), and stays off until next cycle to maintain its average target output current (???)

    • Got intrigued, went back online to find some resources on buck

      • GreatScott video on buck converters, uses Arduino + large breadboard-able parts to demonstrate switching converter solution, good review also cool Arduino demo

        • Most basic form of switching regulation: pure PWM; modulate the Arduino pin at a high frequency with 50% duty cycle to drop the voltage down to half (5V → 2.5V in this case)

        • To do a higher voltage, bring in a FET to be able to handle external source voltage and faster switching frequency

        • Bring in an inductor to resist changes in current - switch ON, source conducts

        • switch OFF, inductor changes polarity and continues current output, flowing through load and diode back to the inductor

          • This diode useful so as to not conduct when buck is switched ON

        • When the inductor is appropriately sized (H) and the PWM frequency is high enough, the inductor is not allowed to fully collapse its magnetic field before the next switch ON cycle… giving a nice rough output at a specified voltage and current

        • clean this output up with a good capacitor

        • lastly, feedback voltage divider is used to send back to the arduino and create a function to continuously check and adjust output duty cycle to hit the appropriate target V or I

    • TI applications notes on calculating buck efficiency

      • Power in a buck converter is primarily lost in the following manners

        • Inductor conduction losses due to Equivalent Series Resistance (DC Resistance)

        • MOSFET conduction losses due to RDS_ON (R value of the FET when conductive) (essentially it’s parasitic resistance)

        • MOSFET switching losses

    • Differences in inductor cores (talking to Ian and Meghan and got curious)

      • Air core (or ceramic core)

        • higher Q value - more precise, better at higher frequencies (RF circuits!)

        • not very good at storing electromagnetic field (EMF).

      • Ferrite and iron core (lumping these together…)

        • very small metal oxide pieces pressed (“sintered”) into a solid block

        • lower Q value - effects optimized for lower on the frequency spectrum (less precise)

        • very good at storing electromagnetic field (EMF)

        • when fully saturated, inductance falls off sharply

      • Powder core

        • Metallic particles suspended and separated by insulating binder material, is a hybrid of features between air core and iron core

        • lower Q value

        • more losses at higher frequencies

        • better DC bias performance than ferrite core

        • Can have low losses in energy at low frequencies

        • soft saturation, where inductance reduces progressively

        • preferred for SMPS and non RF-circuits

    • Differences in capacitor DC bias ratings

      • Class II MLCCs have cheaper dielectrics than Class I (COG/NP0)

      • Lends them to thermally derate as well as derate when significant DC voltage applied (DC bias in capacitors!)

      • COG/NP0 built different, no derating but quickly becomes very expensive at higher F values

      • Electrolytic capacitors don’t derate much at all

Week 10

  • Finished bringing up and validated Single Servo Driver boards 3x

    • Work outlined in Single Servo Driver Test Plan

      • Basic continuity tests with DMM

        • LDO testing 5V to 3.3V rail

      • Efficiency testing with e-load and DMM

      • Input transient testing with 6S batteries

        • soldering XT connectors

  • Reviewed 12V -> 5V @ 4A Buck Converter + ELRS Board and USB-C Sink

    • Minor changes to the ELRS board in layout, 3D body fixes and silkscreen improvements

    • Finished variants for USB-C Sink to cover all voltage values

    • exporting gerbers for both boards, WARG JLCPCB

      • examining pricing for PCB + assembly at JLC, via sizing requirements

    • Redid via layout for both boards to accommodate free JLC via sizing

    • Re-validated flashing viability of the ESP32-C3 on the ELRS board

      • GPIO9

  • Produced End User Manuals for both ELRS and Sink boards

  • Assisted with design on other boards (new buck design for 6S Servo & M3 Tracking Antenna, LED current limiting resistor selection)

  • Researched on ESC functionality, basic design, AM32 firmware

    • More understanding on the system level functionality of drones

Week 11

Week 12

  • Lots of progress on layout for https://uwarg-docs.atlassian.net/wiki/spaces/EL/pages/2701197313

    • 4-layer configuration is extremely tight for routing all of the GPIO but may be doable w/ 6mil traces

    • Created guard ring for the board edges, connected to chassis ground

    • Nearly done, aiming to be done next week and reviewed after

    • Jerry highlighted issue with modem - too little bands for NA (EU/Asia model was selected)

    • Coordinated returning the 3x modems we preemptively purchased to Sarah

    • Documented in project doc several new options for modem

      • Looking at regional LTE bands for speed and best performance long-range

      • One model announced in Aug 2024 has what we need but is unavailable to purchase

    • Researching new TVS diodes to help streamline routing for SIM connectors

      • Standoff Voltage, Breakdown Voltage, Clamp Voltage, Junction Capacitance

  • Coordinated JLCPCB stencil pickup with Sarah/WEEF

    • Our package got turned around 3 times because we didn’t pay customs fees

      • This should be documented!

    • UPS Tracking # is hidden inside of the shipping status on JLCPCB’s website and should just be forwarded to Sarah for good measure as well.

  • Interview prep!

    • Learning operational amplifier basics again (since the beginning of the work term)

    • Understanding the digital logic behind DACs and ADCs

      • Flash ADCs, R-2R (Ladder) DACs, Successive Approximation Register (SAR) ADCs

    • Implementing a current sense circuit for a hypothetical motor controller application