Introduction

• Who

  • @Daniel Puratich Architecture & Management

  • @Kenny Na EE Designer, Documentation

• What

  • USB-C to XT30 adapter to deliver up to 100W (20V 5A) to a drone during stationary testing.

    • Configuration identifiable on the board via circled value on backside silkscreen.

  • PD arbitration handled by the TPS25730; power configuration with resistor dividers on ADC pins.

  • Excludes the use of a microcontroller or dedicated buck/boost converters to save on BOM cost.

End User Guide

USB-C Sink End User Manual

Resources

USB-C Sink | Altium 365

USB-C Power Delivery Hardware Design - Phil's Lab #104

PicoPD - USB-C PD 3.0 PPS Trigger with RP2040

https://www.ti.com/interface/usb/type-c-and-power-delivery/products.html#1241=PD%20controller&

TI | ESD and Surge Protection for USB Interfaces

https://www.usb.org/usb-charger-pd

Wikipedia | USB-C Debug Accessory Mode

TPS25730: Excess Load Capacitance

Field-effect transistor

https://www.robot-electronics.co.uk/i2c-tutorial

https://microchip.my.site.com/s/article/USB-Type-C-Layout-Recommendations#:~:text=USB%20Type%2DC%20CC%20Signals,traces%20with%2050%CE%A9%20impedance.

Engineering

PD Controller Selection

Main Options

There were a few possible options that were selected from research:

• https://www.digikey.ca/en/products/detail/stmicroelectronics/STUSB4500QTR/9092189

• https://www.digikey.ca/en/products/detail/texas-instruments/TPS25730SRSMR/22147461/https://www.digikey.ca/en/products/detail/texas-instruments/TPS25730DREFR/22147394?s=N4IgTCBcDaIC4AcDOYCsB2AzABgCYgF0BfIA

• https://www.digikey.ca/en/products/detail/infineon-technologies/CYPD3177-24LQXQT/10238323

• Cheap PMIC + RP2040 (ex. https://www.digikey.ca/en/products/detail/onsemi/FUSB302B10MPX/7356099 + https://www.digikey.ca/en/products/detail/raspberry-pi/SC0914-13/14306010?s=N4IgTCBcDaIEoAUwAYAsyQF0C%2BQ)

Decision Matrix

The TPS25730x was selected for its recent release, comprehensive datasheet, relatively low price, and simple implementation.

FET Selection

A typical USB-C PD controller will require a gate to block the USB-C input voltage while arbitration occurs. Once the negotiation is successful, the controller sends voltage to the gate to enable the transport of power.

In the case that PD negotiation fails, there is sometimes a fallback “safe power” rail. These might typically supply 5V @ 900mA, or similar. The TPS25730x includes this feature - however, its open drain output pins do not respond to regular USB power events (only those matching the USB-PD protocol).

The TPS25730S recommends the https://www.digikey.ca/en/products/detail/texas-instruments/CSD87501L/5126233, while the TPS25730D comes with an integrated gate in the package. Given the small price delta between the S and D models, the TPS25730D is a practical choice, and very simply concludes our FET selection.

https://www.digikey.ca/en/products/detail/texas-instruments/TPS25730DREFR/22147394?s=N4IgTCBcDaIC4AcDOYCsB2AzABgCYgF0BfIA

Surge Protection

Inrush Current Protection

Open

From the Capacitor section in the TPS25730 datasheet.

Seeing as this board is primarily intended for debugging https://uwarg-docs.atlassian.net/wiki/spaces/EL/pages/2701197313, which includes a buck converter with large bulk capacitance, inrush current protection is required, as recommended by USB-IF. This is due to the capacitors on the load device requesting a large amount of current, characterized by I_cap = C_cap x dV/dt.

As shown above, the TPS25730 datasheet states that inrush current limiting is “implemented as described” in the USB3.2 specification. However:

Open

This information was given to us shortly after the USB-C Sink device was finalized for board order. The board, as a result, does NOT have inrush current limiting implemented. The ESR of the capacitors on the sink device must be high enough to prevent this from being an issue.

The exact section of the USB 3.2 spec regarding inrush currents is shown below.

Input Voltage Protection

While the source device should do most of the voltage regulation, TI recommends a transient voltage suppressing diode be implemented on the VBUS_IN rail. This is due to the possibility of a voltage surge when a cable with current actively running through it is unplugged, causing inductive ringing (as mentioned here), as well as any electrostatic discharge events. For example, the TVS2200 product is recommended for a 20V spec. The Altium schematic is configured with variants, which will change the TVS diode model to match the negotiated voltage.

Power Configuration

Resistor Dividers

The TPS25730 has 4 ADCIN pins that each control a parameter of the requestable voltage and current. Each divider must take voltage from LDO_3V3 and step it down to a target value to be read by the pin. The specific ratios translating to the decoded values are shown in the table below.

The ratio is calculated using: Ratio = R_down / (R_up+R_down).

Decoded ADC Values

If the source device cannot supply voltage between the minimum and maximum voltages set by pins ADCIN1 and ADCIN2 OR the operating/maximum current is violated, then the controller will signal a capabilities mismatch and run the CAP_MIS pin high.

Schematic

Rapid fire notes on the USB PD IC schematic:

• TVS2200 for 20V model, clamping begins at 22V. TVS1400 for 12V model, clamping begins at 14V.

• the LDO_3V3 output pin from the IC is linked to the GPIO pins (e.g. PLUG_FLIP), and can only supply max 5mA, with 1mA max per GPIO pin

• I2C line is likely to be unused and will be DNP’ed during assembly. The PD IC is not power configurable through this line.

The ADC pins are configured as Variants in Altium and are viewable through the Altium 365 project viewer.

Layout

Some notable decisions:

• CC pins are trace width impedance matched to 50 Ohms on the bottom layer.

  • Routing them on the bottom layer makes it so that there is no via stub. It also means the traces have to be wider, as there is no coupling below. Seeing as they will also carry power for VCONN, these were OK to be made wide.

  • The lines are routed in such a way that they will NOT cross a plane split in the board to reduce concern of EMI. As a direct example, CC2 (the lower pin) goes around the VBUS pour and and only where ground would otherwise be. There are ground vias placed near the traces when possible.

• Drain pour is connected to the bottom layer.

  • The DRAIN pins on the TPS25730 are part of the internal FETs on the IC package. Since these will spend the most of their operating time closed, it’s a good idea to give the heat-generating power loss from R_{DS_ON} a thermally conductive pad to be able to leave the board quickly. Vias are placed as recommended by TI.

• USB-C VBUS input routing is on the top and bottom layers.

  • The VBUS input runs through L1/L4, connected through six vias for up to 20V 5A max power draw. While each 8mil hole/16mil diameter via should do around 1.7A, six is recommended by TI and is a good conservative count.

  • Top and bottom layers are exposed to the air, making them the most thermally conductive and are great to route high power nets on. This is due to how current limits on PCBs are often actually thermal limits.

PCB Design

• Input/output connectors labelled for a pleasing aesthetic presentation.

  • Inverted text silkscreen for better readability.

• I2C lines (SCL, SDA) and GND test points are labelled on the back to save space.

• Voltages are labelled on the back of the board. This is so that after assembly, the appropriate voltage configured on the specific board can be circled by sharpie for easy identification.

• Horse on a chair sitting on a porch, viewing a storm. Hard image.

  • This was actually hard to get into Altium - in order to reduce lag and have the appearance of greys, the image was downscaled to 350px and then converted to greyscale and dithered with Floyd-Steinberg algorithm (Normal mode) in GIMP.