terminology

• ZP = zero piolet SW

• DUT = device under test

Architecture Diagram

Open

Component Description

Main Computer (MC)

• 2 components: TEST Case & Analysis Engine

Main Computer - Test case

• user entry point

• prepare data for the driver (transform test cases into UART)

Main Computer - Analysis engine

• Assertions

Driver

• a nucleo board

• enumlate real signal format (PPM, GPS) from TEST case UART input

• inface with TestCase using 1 UART port

• have parallel port connecting to DUT (signal)

• Driver have a buffer to store UART data

sequence diagram

Interface design:

Main computer → driver

• 1 uart will be enough because nucelo is just for single purpose no calculation

• Data Packet Format

receiver → Main computer

• 1 uart will be enough because nucelo is just for single purpose no calculation

• Data Packet Format

main computer(Test Case) ← main computer (

the interface between computer and driver

• option 1: computer send the data at a fixed frequency

• option 2: when nucleo

Open

Question:

How to display the assertion?

reach goal

• GDB-like debugger that explain where it went wrong in the code base in DUT