Power MOSFETs (Jason)
- Jason Skells
- Kevin Li
- Muhammad Tanveer
MOSFET Structure
Trench MOSFETs are mainly used for <200V due to their higher channel density and thus lower on-resistance. Planar MOSFETs are good for higher voltage ratings since on-resistance is dominated by epi-layer resistance and high cell density is not beneficial.
Breakdown Voltage
The breakdown voltage of an insulator is the minimum voltage that causes a portion of an insulator to become electrically conductive.
In the datasheet, BVDSS is usually defined as the drain to source voltage when leakage current is 250uA. The leakage current flowing between source and drain is denoted by I_DSS. It is measured at 100% of the BVDSS rating. As temperature increases, I_DSS increases and BVDSS also increases for power MOSFETs
The breakdown voltage, BVDS, of a FET transistor is the drain-source voltage, VDS, which causes the transistor to enter the breakdown region; this is the region where the transistor receives too much voltage across its drain-source terminal, which causes the drain-source terminal to break down, which makes the drain current, ID, drastically increase.
Drain Current: IDSS (referred to as the drain current for zero bias) is the maximum current that flows through a FET transistor, which is when the gate voltage, VG, supplied to the FET is 0V.
On-State Characteristics
A power MOSFET can be under two different modes of operations: the first quadrant operation and the third quadrant operation.
For an n-channel MOSFET, the device operates in the first quadrant when a positive voltage is applied to the drain, as shown in the figure below. As the gate voltage (VG) increases above the threshold voltage (VTH), the MOSFET channel begins to conduct current. The amount of current it conducts depends on the on-resistance of the MOSFET, as defined by RDSON = VD/ID.
For sufficiently large gate overdrive (VG >> VTH), the ID-VD curve appears linear because the MOSFET channel is fully turned on. Under low gate overdrive, the drain current reaches a saturation point when VD > (VG-VTH) due to a pinch-off effect of the channel.
For a trench MOSFET, R_DSON consists of the following components:
R_S: source resistance
R_CH: channel resistance
R_ACC: resistance from the accumulation region
R_EPI: resistance from the top layer of silicon (epitaxial silicon, also known as epi); epi controls the amount of blocking voltage the MOSFET can sustain
R_SUBS: resistance from the silicon substrate on which the epi is grown
For a planar MOSFET, the RDSON components are similar to that of a trench MOSFET. The primary difference is the presence of a JFET component. As devices scale down to smaller dimensions, RS, RCH, RACC are reduced because more individual unit cells can be packed in a given silicon area. RJFET on the other hand suffers from a “JFET”-effect where current is constrained to flow in a narrow n-region by the adjacent P-body region. Due to the absence of RJFET, trench MOSFETs benefit from high density scaling to achieve very low RDSON.
Threshold Voltage
Threshold voltage, VGS(TH), is defined as the minimum gate bias which can form a conducting channel between the source and drain. For power MOSFETs, it is usually measured at the drain-source current of 250uA. Typically, 2-4V is designed for gate drive of 10-15V. The threshold voltage of the MOSFET decreases as its temperature increases.
Transconductance
Transconductance, gfs, which is defined as the gain of the MOSFETs, can be expressed as the following equation:
It is usually measured at saturation region with fixed VDS. The transconductance is influenced by gate width (W), channel length (LCH), mobility (μn), and gate capacitance (COX) of the devices. gfs decreases with increasing temperature due to the decreasing carrier mobility.
Third-Quadrant Operation
Third-quadrant operation for power MOSFET is common in DC-DC buck converters, where current conduction occurs under at V_DS (for n-channel MOSFET). Current flows in the reverse direction compared to the first-quadrant operation.
Under relatively low current, the on-state characteristics for the third-quadrant operation are symmetric to the first-quadrant operation.
Differences only appear under sufficient large current, and therefore sufficient large V_DON.
When V_DON approaches the forward drop voltage of the body diode, the body diode starts to conduct. As a result, the current increases and no current saturation behavior is observed.
Capacitance
A MOSFET’s switching behavior is affected by the parasitic capacitances between the gate-to-source (CGS), gate-to-drain (CGD) and drain-to-source (CDS) capacitances as shown in the diagram below. These capacitances’ values are non-linear and a function of device structure, geometry, and bias voltages.
When the MOSFET is turned on, capacitors CGD and CGS are charged through the gate, so the gate control circuit design must consider the variation in this capacitance. The MOSFET parasitic capacitances are provided in the data sheet parameters as CISS, COSS, and CRSS:
CGD = CRSS
CGS = CISS − CRSS
CDS = COSS – CRSS
CRSS = small-signal reverse transfer capacitance.
CISS = small-signal input capacitance with the drain and source terminals are shorted.
COSS = small-signal output capacitance with the gate and source terminals are shorted.
Gate Charge
The gate charge can be used to estimate switching times of the power MOSFET once the gate drive current is known. It depends only on the device parasitic capacitances. This parameter is also weakly dependent of the drain current, the supply voltage, and the temperature.
*** include the figure 8 test circuit schematic on pg 4 and improve on the explanation ***
Gate Resistance
The power MOSFET gate presents an impedance like an RC network to its gate drive. The equivalent R is referred to as the gate resistance Rg. The gate resistance is caused by the finite resistance of the Polysilicon gate conductors, and the metal and contact structures that route the gate signal to the pad for connection to external package leads.
Turn-on and Turn-off
Power MOSFET datasheets often contain the resistive switching characteristics, which depend on Rg, Ciss and Crss. While practical measurements are influenced by parasitic inductances and gate drive details, we examine the basic physics here.
td(on) – Turn-on Delay Time
This is the time from when Vgs rises over 10% of the gate drive voltage to when the drain current rises past 10% of the specified current. At the moment of td(on), VGS reaches up to the threshold voltage VTH. This period is controlled by the time constant Rg * Ciss.
tr – Rise Time
This is the time between the drain current rising from 10% to 90% of load current. This depends on the VTH, transconductance gFS and the time constant Rg * Crss.
td(off) – Turn-off Delay Time
It is the time from when Vgs drops below 90% of the gate drive voltage to when the drain current drops below 90% of the load current. It is the delay before current starts to transition in the load and depends on Rg * Ciss.
tf – Fall Time
It is the time between the drain current falling from 90% to 10% of load current. This depends on the VTH, transconductance gFS and the time constant Rg* Crss.
Body Diode Forward Voltage
VSD is a measure of the forward voltage drop of the integral body diode, by applying a set current to the source. The applied current is typically 1A and is specified in the datasheet along with the maximum limit of forward voltage drop. The graph below (body diode forward characteristics) shows typical forward I-V characteristics for the diode at two temperatures. For AOS SRFET, the typical VSD is lower than that of a normal MOSFET, with typical value of 0.4V; this low VSD can help to reduce power loss during diode conduction duration. SRFET is therefore an ideal choice for low side FETs for DC-DC conversion, and other applications where a certain period of body diode conduction is needed
Body Diode Reverse Recovery
MOSFET parasitic body diode reverse recovery occurs during diode switching from the on-state to the off-state, because its stored minority charges must be removed, either actively via negative current, or passively via recombination inside the device. There are three dynamic parameters listed in the datasheet for diode reverse recovery:
trr: body diode reverse recovery time
IRM: body diode reverse peak current
Qrr: Body diode reverse recovery charge, defined by the area within the negative portion of the diode current waveform.
*** include the figure 11 test circuit schematic on pg 6 and improve upon this explanation ***
Avalanche capability and ratings
Avalanche capability
When using MOSFETs with inductors, high voltage which exceeds the maximum rating (VDSS) of the MOSFET occurs as a result of back-electromotive force from L when the MOSFET is turned OFF. If the VDSS is exceeded, current will flow despite the MOSFET being in the OFF state and this can damage the MOSFET. The amount of energy that can be tolerated at this time is called the “avalanche capability”.
Physics of avalanche breakdown
As the voltage of a power MOSFET is increased, the electric field increases at the body-epi junction. When this field reaches a critical value EC (about 3E5V/cm in Si), avalanche multiplication of carriers occurs, leading to an abrupt increase in current
Avalanche ratings
Power MOSFETs may be driven to voltages more than the rated VDS(MAX) due to inductive spikes during circuit operation. Therefore, manufacturers commonly specify single and repetitive ratings, and many perform 100% single pulse testing on shipped units.
**can include the repetitive ratings but it doesn’t seem very important to us**
dV/dt ratings
Power MOSFETs fail from excessive drain source dV/dts under various scenarios. In each case, the failure is caused by displacement or conduction current flow via Rp+Rc, leading to turn-on of the parasitic bipolar, and consequent failure of the device by the same mechanism described before for avalanche failures.
If the gate is shorted to source via a resistor, and a fast dV/dt applied between Drain and source, the displacement current Coss*dV/dt flows under the source and can develop sufficient voltage drop across Rp+Rc to exceed the VBE (0.7V) of the parasitic bipolar. Due to the low Coss values of most modern power MOSFETs, this current is low even for dV/dts of 10-50V/ns and is not considered a major failure mode. If, however, the resistance shorting the gate to source is large, the Crss*dV/dt current will develop enough voltage drop across it to turn on the gate, leading to current flow which if unconstrained, can lead to device failure.
During body diode reverse recovery, hole current flows out of the source contact via Rp+Rc. This current adds to and often far exceeds the Coss*dV/dt current at also flows as the voltage develops across the body diode of the FET. Since the diode stored charge and its removal is non-uniform, the diode recovery dV/dt failure is seen at lower values of dV/dt. The failure mechanism is again caused by turn-on of the parasitic bipolar. If the gate-source shorting resistor is too large, there is the further possibility of exacerbating the dV/dt current by turning on the gate of the MOSFET by developing sufficient voltage across the resistor as it sinks the Crss*dV/dt current.
Both modes of dV/dt failure get worse with as the temperature increases.
Thermal Resistance Characterization
Junction Calibration
Before the thermal resistance of any device is to be measured, a calibration curve must be made. Each silicon device has its own unique calibration, but once determined, is valid for any package it may be put into. The calibration curve is measured by treating the device as a diode and forcing a 10mA sense current (IS) and measuring the forward voltage drop (VFSD) at each junction temperature. A sample calibration curve for a device is shown in the graph below (example temperature calibration curve). On subsequent thermal resistance tests, the same 10mA sense current will be forced through the device and the junction temperature will be calculated from the resulting forward voltage drop.
Junction-to-Ambient/Lead/ Case Thermal Resistance
The junction-to-ambient thermal resistance RθJA is defined as the thermal resistance from the device junction to the ambient environment. The junction-to-lead thermal resistance RθJL is the thermal resistance from the device junction to the drain lead of the device. For larger devices (Ultra SO8 and bigger) with a back exposed drain pad, the RθJC must also be measured. RθJC is defined as the thermal resistance from the device junction to the device case. Both can be calculated from the following equation:
Where TJ is the junction temperature of the device, it can be read out from junction calibration curve by measuring forward voltage drop at different junction temperature.
TX is the ambient, lead or case temperature depending on whether RθJA, RθJL or RθJC is being measured.
PD is the power dissipation of the device, which is calculated by input voltage and current.
Power Dissipation
Power dissipation, PD and PDSM, are the maximum power that is allowed for device safe operation. Power dissipation is calculated using the following formula:
PD is based on junction to case thermal resistance. To achieve power dissipation of PD, case temperature needs to be maintained at 25°C.
PDSM is based on junction to ambient thermal resistance. The device is mounted on a 1 square inch 2 oz. copper PCB, and PDSM is the power that raises TJ to 150°C.
Safe-Operating Area (SOA)
Forward Bias Safe-Operating Area curves define the maximum value of drain to source voltage and drain current which guarantees safe operation when the device is in forward bias.
The right-hand vertical boundary is maximum drain to source voltage (VDS).
The upper horizontal limit is maximum pulsed drain current (IDM).
The slope on left had side is limited by drain to source on resistance (RDS(ON)).
The paralleled lines in the middle are the maximum drain to source current for different pulse widths. These currents are determined by the transient thermal impedance.
Current Ratings
Continuous Drain current - ID and IDSM
Excluding package limitations, the continuous Drain Current ID and IDSM is the maximum drain current corresponding to PD and PDSM.
ID will be reduced with increasing case temperature, as shown in the graph above (max forward biased SOA), based on the reduced power dissipation allowed.
Package Limitation
Continuous current rating is limited by two factors:
Thermal resistance
Package limitation
Package limitation usually refers to bond wire current handling capability. The conventional way to rate bond wire current limit is based on bond wire fusing temperature, which is not correct because:
Wire temperature cannot exceed 220°C, or it will cause the degradation of the plastic molding compound.
In most cases the silicon resistance is ~10 times higher than wire resistance. Most of the heat is generated on the silicon surface. The hottest spot is on silicon.
Silicon maximum junction temperature is lower than 220°C, that’s why bond wire fusing problem doesn’t exist in most of the cases. Bond wires fuse only when devices fail.
Pulsed Drain Current - IDM
Pulsed Drain Current is rated for 260μs current pulse. The value on datasheet is the lower value of the following two:
Actual single pulse current measurement with 260μs current pulse.
Calculation based on transient thermal resistance at 260μs pulse duration.